Semiconductor device

ABSTRACT

A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2012-195087 filed onSep. 5, 2012 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device, and moreparticularly to a semiconductor device having, for example, an ACcoupling element.

In order to transmit a signal between semiconductor devices (hereinafteralso called “chips”) to which supply voltages different from each otherare applied, an AC coupling element formed in the semiconductor devicemay be used. As the AC coupling element, there have been known anon-chip transformer including a pair of inductors which is magneticallycoupled with each other, and a coupling capacitance including a pair ofcapacitive electrodes which is capacitively coupled with each other. Inthe present specification, one of the pair of inductors configuring theAC coupling element may be called “first element”, and the otherinductor may be called “second element”. Similarly, the pair ofcapacitive elements may be called “first element” and “second element”.

The first element and the second element configuring the AC couplingelement are structured to face each other through an insulating film.When a high voltage is applied between a primary side and a secondaryside of the AC coupling element, the high voltage is applied between thefirst element and the second element. As a result, there is a concernabout the deterioration of the insulating film caused by the highvoltage, and also insulation breakdown.

Japanese Unexamined Patent Application Publication N Hei5(1993)-13543discloses a configuration in which when a large current flows in a powersupply line due to a pin hole or latch-up of the insulating film, atemperature detection unit detects a rise in the chip temperature, and asupply voltage supply unit breaks a current on the basis of a detectionsignal thereof. U.S. Pat. No. 7,639,021 discloses a configuration inwhich a voltage of a high voltage battery is measured at given intervalsto detect the breakdown of an insulating film. U.S. Pat. No. 8,129,999discloses a configuration in which the insulation breakdown of a stackedcell is detected on the basis of a current that flows in a shuntresistor connected between a high voltage terminal and a ground terminalof the stacked cell. Shunichi Kaeriyama, Shinichi Uchida, MasayukiFurumiya, Mitsuji Okada, Masayuki Mizuno, “A 2.5 kV isolation 35 kV/μsCMR 250 Mbps 0.13 mA/Mbps Digital Isolator in 0.5 μm CMOS with anon-chip small transformer”, 2010 IEEE Symposium on VLSI Circuits, pp.197-198, 2010 discloses a configuration of a transmitter circuit and areceiver circuit of an on-chip transformer.

SUMMARY

When a surge voltage such as an unintentional static electricity isapplied between the primary side and the secondary side of the ACcoupling element, the insulating film that isolates those primary andsecondary sides from each other may be deteriorated. The application ofa high voltage (signal transmission by the AC coupling element) to theinsulating film for a long time breaks the insulating film, therebyleading to a concern about short-circuiting between the primary side andthe secondary side of the AC coupling element, and a function loss ofthe semiconductor device having the AC coupling element. This makes itnecessary to detect the insulation breakdown of the AC coupling elementprovided in the semiconductor device in an initial stage, and to furthersafely shut down a system having the semiconductor device. The otherobjects and novel features will become apparent from the description ofthe present specification, and the attached drawings.

According to an aspect of the present invention, there is provided asemiconductor device including: an AC coupling element formed on asemiconductor substrate; a temperature monitoring unit that outputs atemperature monitor signal in response to a change in a temperature ofthe semiconductor substrate, in which the temperature monitoring unithas a first temperature monitoring element that outputs a temperaturemonitor signal, and the first temperature monitoring element is arrangedin a region immediately below or a region adjacent to the AC couplingelement.

According to the aspect of the present invention, there can be providedthe semiconductor device that detects the insulation breakdown of the ACcoupling element in the initial stage, and further shuts down the systemin safely.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram of a signal transmission module havingfirst and second semiconductor devices according to a first embodiment;

FIG. 2 is a circuit configuration diagram of the first semiconductordevice according to the first embodiment;

FIG. 3 is a circuit configuration diagram of the second semiconductordevice according to the first embodiment;

FIGS. 4A and 4B are configuration diagrams of a temperature monitoringunit installed in the first semiconductor device according to the firstembodiment;

FIGS. 5A and 5B are plan views of an on-chip transformer installed inthe first semiconductor device according to the first embodiment;

FIGS. 6A and 6B are plan views illustrating a layout relationshipbetween the temperature monitoring unit and the on-chip transformerinstalled in the first semiconductor device according to the firstembodiment;

FIGS. 7A and 7B are cross-sectional views of the temperature monitoringunit and the on-chip transformer installed in the first semiconductordevice along an X-X′ direction thereof according to the firstembodiment;

FIGS. 8A and 8B are cross-sectional views of the temperature monitoringunit and the on-chip transformer installed in the first semiconductordevice along a Y-Y′ direction thereof according to the first embodiment;

FIG. 9 is a graph illustrating a change in an insulation resistancevalue when the insulation breakdown between coils of the on-chiptransformer is generated, which has been studied by the presentinventors;

FIGS. 10A and 10B are graphs illustrating a transmission time of heatgenerated in an insulation breakdown portion, which has been studied bythe present invention;

FIGS. 11A and 11B are a plan view and a cross-sectional viewillustrating a mechanism of abnormality detection by the temperaturemonitoring unit (without a shield layer) and a heat generationdetermination unit installed in the first semiconductor device accordingto the first embodiment;

FIGS. 12A and 12B are a plan view and a cross-sectional viewillustrating the mechanism of the abnormality detection by thetemperature monitoring unit (with the shield layer) and the heatgeneration determination unit installed in the first semiconductordevice according to the first embodiment;

FIG. 13 is a circuit diagram of the heat generation determination unitinstalled in the first semiconductor device according to the firstembodiment;

FIGS. 14A and 14B are configuration diagrams of a power supply lineconnected to the heat generation determination unit, the temperaturemonitoring unit, and a transmitter circuit which are installed in thefirst semiconductor device according to the first embodiment;

FIG. 15 is a plan view illustrating a layout of the respectivetemperature monitoring units in the first semiconductor device and thesecond semiconductor device according to the first embodiment;

FIG. 16A and FIG. 16B are circuit diagrams of one example of a referencevoltage generator circuit provided in the heat generation determinationunit which is installed in the first semiconductor device according tothe first embodiment;

FIGS. 17A and 17B are circuit diagrams of another example of thereference voltage generator circuit provided in the heat generationdetermination unit which is installed in the first semiconductor deviceaccording to the first embodiment;

FIGS. 18A to 18D are circuit diagrams illustrating respective variousconfiguration examples of the temperature monitoring unit according tothe respective embodiments;

FIGS. 19A to 19C are circuit diagrams of modifications of the heatgeneration determination unit according to the respective embodiments;

FIGS. 20A and 20B are layout plan views of modifications of thetemperature monitoring unit installed in the first semiconductor deviceaccording to the first embodiment;

FIGS. 21A and 21B are layout plan views illustrating a layoutrelationship between the modification of the temperature monitoring unitinstalled in the first semiconductor device and the on-chip transformeraccording to the first embodiment;

FIG. 22 is a system configuration diagram of a signal transmissionmodule having the first semiconductor device and the secondsemiconductor device according to the first embodiment;

FIG. 23 is a circuit block diagram of the first semiconductor device andthe second semiconductor device installed in the signal transmissionmodule according to the first embodiment;

FIG. 24 is a circuit diagram illustrating another layout example of thetemperature monitoring unit installed in the first semiconductor deviceaccording to the first embodiment;

FIG. 25 is a circuit diagram illustrating another layout example of thetemperature monitoring unit installed in the second semiconductor deviceaccording to the first embodiment;

FIG. 26 is a configuration diagram of a signal transmission modulehaving the first semiconductor device and the second semiconductordevice according to a second embodiment;

FIGS. 27A and 27B are configuration diagrams of a signal transmissionmodule having the first semiconductor device and the secondsemiconductor device according to a third embodiment;

FIG. 28 is a configuration diagram of a signal transmission modulehaving the first semiconductor device, the second semiconductor device,a third semiconductor device, and a fourth semiconductor deviceaccording to a fourth embodiment;

FIG. 29 is a configuration diagram of a semiconductor device accordingto a fifth embodiment; and

FIG. 30 is a configuration diagram of a signal transmission moduleinstalled in the first semiconductor device and the second semiconductordevice according to a sixth embodiment.

DETAILED DESCRIPTION

Hereinafter, embodiments will be described with reference to theaccompanying drawings. In the case where reference is made to the numberand quantity in the description of the embodiments, the invention is notalways limited to specified number and quantity unless explicitly statedotherwise. In the drawings of the embodiments, identical referencesymbols or reference numerals represent the same or corresponding parts.Also, in the description of the embodiments, the redundant descriptionof parts indicated by the identical reference symbols is not repeated.

First Embodiment

A configuration of a signal transmission module MD1 having asemiconductor device LSI1 and a semiconductor device LSI2 according to afirst embodiment will be described with reference to FIG. 1.

The signal transmission module MD1 is configured by an SiP (system inpackage) in which the respective chips of the semiconductor device LSI1and the semiconductor device LSI2 are packed in one package. The signaltransmission module MD1 has multiple leads 2. The leads 2 areelectrically connected to respective pads 3 formed on the semiconductordevice LSI1 and the semiconductor device LSI2 through respective bondingwires 1.

The electric connection means between the pads 3 of the semiconductordevice LSI1 and the semiconductor device LSI2, and the leads 2 is notlimited to the bonding wires 1, but can be appropriately changed.Referring to FIG. 1, the same rectangular patterns not denoted byreference numeral 3 also represent the pads 3, particularly, except forthose denoted by other symbols (P11, P12, and so on).

The semiconductor device LSI1 includes an on-chip transformer OCT1 whichis an AC coupling element, a transmitter circuit TX1, a receiver circuitRX1, a control circuit CTL1, a heat generation determination unit EDET1,a low voltage protection circuit UVLO, and a temperature monitoring unitTS1. The on-chip transformer OCT1 includes a primary coil (not shown)which is any one of a first element and a second element, and asecondary coil (not shown) which is the other of the first element andthe second element. Those circuits are applied with a supply voltageGND1 (for example, 0 V) applied to the leads 2, and a supply voltageVDD1 (for example, 5 V).

A signal In1 supplied to the lead 2 is input to a control circuit CTL1through the bonding wire 1 and the pad 3. As will be described later,the control circuit CTL1 outputs a signal generated on the basis of thesignal In1, and outputs of the low voltage protection circuit UVLO andthe heat generation determination unit EDET1 to the transmitter circuitTX1. The transmitter circuit TX1 current-drives the primary coil of theon-chip transformer OCT1 on the basis of the signal In1. One end of thesecondary coil magnetically coupled with the primary coil is connectedto the pad P11, and the other end of the secondary coil is connected tothe pad P12. An electromotive force is generated between both of thosepads by electromagnetic induction.

The temperature monitoring unit TS1 is formed on the semiconductorsubstrate in the vicinity of the on-chip transformer OCT1. As will bedescribed later, the temperature monitoring unit TS1 is formed of adiode, and an anode and a cathode of the diode are connected to a linesa and a line sc, respectively, and the line sa and the line sc areconnected to the heat generation determination unit EDET1. When aninsulating film between the primary coil and the secondary coil of theon-chip transformer OCT1 is broken down by a high voltage, abnormal heatgeneration is caused by short-circuiting between both of those coils.The temperature monitoring unit TS1 converts a change in the temperatureof the semiconductor substrate caused by the abnormal heat generationinto a change in a forward voltage of the diode, and outputs the voltageto the heat generation determination unit EDET1 through the line sa.Hereinafter, the voltage across the line sa is called “temperaturemonitor signal sa”.

The semiconductor device LSI2 includes an on-chip transformer OCT2 whichis an AC coupling element, a transmitter circuit TX2, a receiver circuitRX2, an IGBT (integrated gate bipolar transistor) driver circuit DRV, anIGBT overcurrent detection unit OCD, an IGBT overheat detection unitOHD, the low voltage protection circuit UVLO, a heat generationdetermination unit EDET2, and a control circuit CTL2. Those circuits areapplied with the supply voltage GND2 (for example, 0 to 500 V) to beapplied to the leads 2, and the supply voltage VDD2 (for example, GND2+5V).

The transmitter circuit TX2 controls a current flowing in the primarycoil (not shown) of the on-chip transformer OCT2. One end of thesecondary coil (not shown) magnetically coupled with the primary coil ofthe on-chip transformer OCT2 is connected to a pad P21, and the otherend of the secondary coil is connected to a pad P22. The receivercircuit RX2 is applied with voltages of the pad P11 and the pad P12 ofthe semiconductor device LSI1. The IGBT driver circuit DRV outputs adrive signal IGDry to a gate of an IGBT (not shown) on the basis of anoutput of the receiver circuit RX2.

A temperature monitoring unit TS2 which is a diode is formed on thesemiconductor substrate in the vicinity of the on-chip transformer OCT2.An anode and a cathode of the diode are connected to the line sa and theline sc, respectively. The line sa and the line sc are connected to theheat generation determination unit EDET2. Like the temperaturemonitoring unit TS1, the temperature monitoring unit TS2 detects anabnormal heat generation caused by the abnormal heat generation causedby the insulating film breakdown in the on-chip transformer OCT2, andoutputs the temperature monitor signal sa to the heat generationdetermination unit EDET2.

The IGBT overcurrent detection unit OCD detects whether an overcurrentis generated in the IGBT, or not, on the basis of a signal Csengenerated in a current monitoring circuit of the IGBT not shown. TheIGBT overheat detection unit OHD detects whether abnormal overheat isgenerated in the IGBT or not on the basis of a signal Temp generated bytemperature measurement means of the IGBT not shown. As will bedescribed later, the control circuit CTL2 outputs a signal to thetransmitter circuit TX2 and the IGBT driver circuit DRV on the basis ofoutputs of the IGBT overcurrent detection unit OCD, the IGBT overheatdetection unit OHD, and the low voltage protection circuit UVLO.

A circuit configuration of the semiconductor device LSI1 according tothe first embodiment will be described with reference to FIG. 2.

The transmitter circuit TX1 generates a drive current in a primary coilL11 of the on-chip transformer OCT1 on the basis of an output signal ofthe control circuit CTL1. One end of a secondary coil L12 magneticallycoupled with the primary coil L11 is connected to the pad P11, and theother end of the secondary coil L12 is connected to the pad P12. Thereceiver circuit RX1 outputs a signal Rxo1 on the basis of a signal In11and a signal In12 which are output from the secondary coil of theon-chip transformer OCT2 in the semiconductor device LSI2.

The temperature monitoring unit TS1 is arranged immediately below or inthe vicinity of the on-chip transformer OCT1. One end of the temperaturemonitoring unit TS1 is connected to the heat generation determinationunit EDET1 through the line sa, and the other end of the temperaturemonitoring unit TS1 is applied with the supply voltage GND1 through theline sc. The supply voltage VDD1 and the supply voltage GND1 of thesemiconductor device LSI1 are applied with the supply voltage VDD1 andthe supply voltage GND1, respectively.

The heat generation determination unit EDET1 outputs a heat generationdetection signal Err1 indicative of the abnormal heat generation in anon-chip transformer OCT1 formation region on the basis of thetemperature monitor signal sa. When the abnormal heat generation isdetected, the heat generation determination unit EDET1 changes the heatgeneration detection signal Err1 from a low level (supply voltage GND1)to a high level (supply voltage VDD1). When the supply voltage VDD1drops to a given value or lower, the low voltage protection circuit UVLOchanges the output signal from the low level to the high level.

The control circuit CTL1 is configured by a gate circuit 101, andoutputs a logical operation (AND) result of the signal In1, a signalRxo1, an output signal of the low voltage protection circuit UVLO, andthe heat generation detection signal Err1 to the transmitter circuitTX1. As will be described later, the signal Rxo1 is a signal indicativeof the occurrence of abnormal operation of the IGBT driven by thesemiconductor device LSI2. Therefore, when the signal transmissionmodule MD1 operates normally, all of the signal Rxo1, the output signalof the low voltage protection circuit UVLO, and the heat generationdetection signal Err1 become low level, and the control circuit CTL1generates the signal to be output to the transmitter circuit TX1 on thebasis of the signal In1.

On the other hand, when the abnormal overheat is generated in theon-chip transformer OCT1 due to the insulating film breakdown betweenthe primary coil L11 and the secondary coil L12 of the on-chiptransformer OCT1, and also short-circuiting between those coils, theheat generation determination unit EDET1 sets the heat generationdetection signal Err1 to the high level. The control circuit CTL1controls the operation of the transmitter circuit TX1 on the basis of achange in the heat generation detection signal Err1.

A circuit configuration of the semiconductor device LSI2 according tothe first embodiment will be described with reference to FIG. 3.

The transmitter circuit TX2 generates a drive current in a primary coilL21 of the on-chip transformer OCT2 on the basis of an output signal Ct2of the control circuit CTL2. One end of a secondary coil L22magnetically coupled with the primary coil L21 is connected to the padP21, and the other end of the secondary coil L22 is connected to the padP22. The receiver circuit RX2 outputs a signal Rxo2 on the basis of asignal In21 and a signal In22 which are output from the secondary coilof the on-chip transformer OCT1 in the semiconductor device LSI1. TheIGBT driver circuit DRV outputs the drive signal IGDry to the gate ofthe IGBT not shown, on the basis of the signal Rxo2. The temperaturemonitoring unit TS2 is arranged immediately below or in the vicinity ofthe on-chip transformer OCT2. One end of the temperature monitoring unitTS2 is connected to the heat generation determination unit EDET2 throughthe line sa, and the other end of the temperature monitoring unit TS2 isapplied with the supply voltage GND2 through the line sc.

A temperature detection unit 30 is arranged in the vicinity of the IGBTdriver circuit DRV. The temperature detection unit 30 detects atemperature in the vicinity of an output stage of the IGBT drivercircuit DRV. When the drive current of the IGBT driver circuit DRVexcessively increases, and a temperature of the semiconductor substrateexceeds a given value, the control circuit CTL2 shuts down thesemiconductor device LSI2. With this shut-down, the thermal destructionof the semiconductor device LSI2 is avoided in advance.

The heat generation determination unit EDET2 outputs a heat generationdetection signal Err2 indicative of the abnormal heat generation in anon-chip transformer OCT2 formation region, on the basis of thetemperature monitor signal sa. When the heat generation determinationunit EDET2 detects the abnormal heat generation, the heat generationdetermination unit EDET2 changes the heat generation detection signalErr2 from the low level (supply voltage GND2) to the high level (supplyvoltage VDD2). The IGBT overcurrent detection unit OCD detects anovercurrent generation in the IGBT on the basis of an output signal Docdfrom an emitter current monitoring circuit (not shown) of the IGBT, andchanges an output signal thereof from the low level to the high level.The overheat detection unit OHD detects an abnormal temperature rise inthe IGBT on the basis of an output signal Dohd from a temperaturemonitoring circuit (not shown) of the IGBT, and changes an output signalthereof from the low level to the high level. When the supply voltageVDD2 drops to a given value or lower, the low voltage protection circuitUVLO changes the output signal from the low level to the high level.

The control circuit CTL2 is configured by a gate circuit 201, andoutputs a signal Ct2 which is a logical operation (AND) result of theheat generation detection signal Err2, an output of the overcurrentdetection unit OCD, an output of the overheat detection unit OHD, and anoutput of the low voltage protection circuit UVLO to the transmittercircuit TX2 and the IGBT driver circuit DRV. In the IGBT driven by thesignal transmission module MD1 having the semiconductor device LSI2,when overcurrent or the abnormal overheat is detected for some cause,the control circuit CTL2 controls the IGBT driver circuit DRV accordingto the signal Ct2, and also notifies the semiconductor device LSI1 ofthe abnormality generation through the transmitter circuit TX2 and theon-chip transformer OCT2.

A configuration of the temperature monitoring unit TS1 installed in thesemiconductor device LSI1 according to the first embodiment will bedescribed with reference to FIGS. 4A and 4B.

FIG. 4A is a layout plan view of the temperature monitoring unit TS1.The temperature monitoring unit TS1 is configured by multiple pnjunction diodes (temperature detection elements) formed on thesemiconductor substrate, and each of the pn junction diodes has an anode(p-type impurity region) A and a cathode (n-type impurity region) C.FIG. 4A illustrates a structure of a horizontal pn junction diode, whichmay be replaced with a vertical pn junction diode in which the n-typeimpurity region (cathode) formed on the semiconductor substrate isreplaced with the p-type impurity region (anode).

As will be described later, pn junction diodes Du1 to Du8 are formedimmediately below the on-chip transformer OCT1, a pn junction diode Dcis formed in the center thereof, and a pn junction diode Do is formed inan outer periphery thereof. The pn junction diodes Du1 to Du8, therespective anodes A of the Dc are connected to a line sa1, and therespective cathodes C is connected to a line sc1. An anode A and acathode C of the pn junction diode Do are connected to line sa2 and linesc2, respectively. The line sa1, the line sc1, the line sa2, the linesc2, a line tx11, a line tx12, a line sld1, and a line sld2 are formedof, for example, a first wiring layer.

FIG. 4B is an equivalent circuit diagram of the temperature monitoringunit TS1 illustrated in FIG. 4A. The pn junction diodes Du1 to Du8, andthe pn junction diode Dc are connected in parallel between the line sa1and the line sc1 in a first system, and the pn junction diode Do isconnected to the line sat and the line sc2 in a second system.

A configuration of the on-chip transformer OCT1 installed in thesemiconductor device LSI1 according to the first embodiment will bedescribed with reference to FIGS. 5A and 5B.

The on-chip transformer OCT1 has a configuration in which the respectivecoils are formed of a lower wiring layer and an upper wiring layer onthe semiconductor substrate, and the respective coils are isolated fromeach other by an interlayer insulating film. FIG. 5A illustrates a lowerwiring layer pattern which forms the primary coil L11 of the on-chiptransformer OCT1, and the lower wiring layer pattern is formed of, forexample, a second wiring layer. Both ends of the primary coil L11 areconnected to the transmitter circuit TX1 through the line tx11 and theline tx12 (not shown). A shield layer S1 is formed in the center of theprimary coil L11. A shield layer S2 and a shield layer S3 are formed inan outer periphery of the primary coil L11.

Aside from the on-chip transformer OCT1, a line sa12, a line sc12, and aline sld12 are formed of the second wiring layer. Respective via holesv12 for connection to the first wiring layer are formed in theinterlayer insulating film on both ends of the respective linessurrounded by dashed rectangles. The shield layer S2 is connected to theline sld2 (refer to FIG. 4B) through the via holes v12. The shield layerS1 and the shield layer S3 are connected to the line sld1 throughrespective via holes v12.

FIG. 5B illustrates the upper wiring layer pattern that forms thesecondary coil L12 of the on-chip transformer OCT1, and the upper wiringlayer pattern is formed of, for example, a fifth wiring layer. One endof the secondary coil L12 is connected to the pad P11 formed of thefifth wiring layer in the center thereof, and the other end of thesecondary coil L12 is connected to the pad P12 formed of the fifthwiring layer in the outer periphery of the secondary coil L12. Theshield layer S1 and the shield layer S2 are formed to overlap with thepad P11 and the pad P12, respectively.

A layout relationship between the temperature monitoring unit TS1 andthe on-chip transformer OCT1 installed in the semiconductor device LSI1according to the first embodiment will be described with reference toFIGS. 6A and 6B.

FIG. 6A is a plan view of a configuration in which the first wiringlayer overlaps with the second wiring layer forming the primary coil L11of the on-chip transformer OCT1. Both of the shield layer S1 and theshield layer S3 are connected to the line sld1 through the respectivevia holes v12. The shield layer S2 is connected to the line sld2 throughthe via hole v12. The line sld1 and the line sld2 are connected to theline sld12, which is applied with the supply voltage GND1, through therespective via holes v12. That is, the shield layers S1 to S3 areapplied with the supply voltage GND1.

Both of the line sa1 and the line sa2 connected to the line sa12 throughthe respective via holes v12 are connected to the line sa. Both of theline sc1 and the line sc2 connected to the line sc12 through the viaholes v12 are connected to the secondary coil. The line sa is connectedto the heat generation determination unit EDET1, and the secondary coilis applied with the supply voltage GND1.

FIG. 6B illustrates a layout relationship between the respective pnjunction diodes, and the shield layers S1 to S3 configuring thetemperature monitoring unit TS1. The shield layer S1 is formed to coverthe pn junction diode Dc formed in the center of the on-chip transformerOCT1, and the line sa1 and the line sc1 connected to the pn junctiondiode Dc. The shield layer S2 is formed to cover the diode Do arrangedin the outer periphery of the primary coil L11, and the line sa2 and theline sc2 connected to the diode Co. The shield layer S3 is arranged tocover the line sa1, the line sc1, the line tx11, and the line tx12 (allof those lines are formed of the first wiring layer) in the vicinity ofthe on-chip transformer OCT1.

A description will be given of a cross-sectional view of the temperaturemonitoring unit TS1 and the on-chip transformer OCT1 installed in thesemiconductor device LSI1 in an X-X′ direction thereof according to thefirst embodiment with reference to FIGS. 7A and 7B.

FIG. 7A is a plan view of the on-chip transformer OCT1 formed on thesemiconductor substrate having the temperature monitoring unit TS1. FIG.7A illustrates the secondary coil L12, the pad P11, and the pad P12,which are formed of the fifth wiring layer, and the primary coil L11 andthe shield layers S1 to S3, which are formed of the second wiring layer.

FIG. 7B illustrates a cross-sectional view taken along a line X-X′ inFIG. 7A. A pn junction diode Du4 and a pn junction diode Du8 are formedon a semiconductor substrate Sub in a region immediately below theon-chip transformer OCT1. The pn junction diode Dc is formed on thesemiconductor substrate Sub in a center surrounded by the on-chiptransformer OCT1 formation region. Each of the pn junction diodes hasthe anode A and the cathode C. The respective anodes A and cathodes Care connected to the line sa1 and the line sc1 formed of a first wiringlayer M1 through a contact cnt, respectively. In the cross-sectionalview taken along a line X-X′ in FIG. 7B, the line sa1 and the contactcnt may not be shown in relation to the position and the direction ofthe respective pn junction diodes.

A second wiring layer M2 is formed over an upper layer of the firstwiring layer M1 through an insulating layer. The primary coil L11 of theon-chip transformer OCT1, the shield layer S1, and the shield layer S3are formed of the second wiring layer M2. The primary coil L11 isconnected to the line tx12 of the transmitter circuit TX1, which isformed of the first wiring layer that allows the drive current to flowtherein, through the via hole v12. The shield layer S1 is formed tocover the line sa1 connected to the anode A of the pn junction diode Dc.The shield layer S3 is formed to cover the line sa1, the line sc1, theline tx11, and the line tx12 in the vicinity of the on-chip transformerOCT1.

The secondary coil L12 of the on-chip transformer OCT1, and the pad P11,which are formed of a fifth wiring layer M5, are formed above an upperlayer of the second wiring layer M2 through an insulating layer. Theon-chip transformer OCT1 is about 300 μm in diameter, and formed at aheight of about 5 to 30 μm from the semiconductor substrate Sub. In FIG.7B, the insulating layer between the first wiring layer M1 and thesecond wiring layer M2, and the insulating layer between the secondwiring layer M2 and the fifth wiring layer M5 are formed between therespective wiring layers, with the use of a material, a thickness, and amanufacturing process which are appropriately selected.

A description will be given of a cross-sectional view of the temperaturemonitoring unit TS1 and the on-chip transformer OCT1 installed in thesemiconductor device LSI1 in a Y-Y′ direction thereof according to thefirst embodiment with reference to FIGS. 8A and 8B.

FIG. 8A illustrates the same plan view as that of FIG. 7A. FIG. 8Billustrates a cross-sectional view taken along a line Y-Y′ of FIG. 8A. Apn junction diode Du2 and a pn junction diode Du6 in a regionimmediately below the on-chip transformer OCT1, the pn junction diode Dcin the center thereof, and the pn junction diode Do in the outerperiphery thereof are formed on the semiconductor substrate Sub. Theanode A and the cathode C of the respective pn junction diodes areconnected to the line sa1 and the line sc1, which are formed of thefirst wiring layer M1, through the contact cnt.

The second wiring layer M2 is formed over the upper layer of the firstwiring layer M1 through the insulating layer. The primary coil L11 ofthe on-chip transformer OCT1, the shield layer S1, and the shield layerS2 are formed of the second wiring layer M2. The shield layer S1 isformed to cover the line sa1 and the line sc1 connected with the pnjunction diode Dc, and the shield layer S2 is formed to cover the linesa2 and the line sc2 which are connected to the pn junction diode Do.The secondary coil L12 of the on-chip transformer OCT1, the pad P11, andthe pad P12, which are formed of the fifth wiring layer M5, are formedover the upper layer of the second wiring layer M2 through theinsulating layer.

The pn junction diode Du2, the pn junction diode Dc, and the pn junctiondiode Do are arranged in the region immediately below, in the center of,and in the outer periphery of the on-chip transformer OCT1,respectively. The region immediately below the on-chip transformer OCT1represents a region of the semiconductor substrate immediately below aportion where the primary coil L11 or the secondary coil L12 is formed.The center represents a region of the semiconductor substrate which issurrounded by the region immediately below the on-chip transformer OCT1.The outer periphery represents a region in the outer periphery of theregion immediately below the on-chip transformer OCT1. The center andthe outer periphery are collectively called “adjacent regions of theon-chip transformer OCT1”.

As will be described later, when a high voltage continues to be appliedbetween the primary coil L11 and the secondary coil L12 for a long time,the insulating film that isolates those coils from each other may bebroken down. When the insulating film is broken down, a short-circuitingcurrent between the primary coil L11 and the secondary coil L12 isgenerated in the breakdown portion. The generation of theshort-circuiting current a rapid rise in the temperature of thebreakdown portion of the insulating film, and the semiconductorsubstrate in the vicinity of the breakdown portion. The pn junctiondiode Do and the pn junction diode Dc are arranged in the adjacentregion. The pn junction diode Do and the pn junction diode Dc, which arearranged in the adjacent region, detect the rapid rise in thetemperature of the semiconductor substrate caused by theshort-circuiting current substantially at the same time as that of thepn junction diode Du2 arranged in the region immediately below theon-chip transformer OCT1.

A description will be given of a temporal change in an insulationresistance value when the insulation breakdown is generated between thecoils of the on-chip transformer, which has been studied by the presentinventors, with reference to FIG. 9.

The axis of abscissa represents a time of an arbitrary scale, and theaxis of ordinate represents a resistance value of the insulating filmbetween the primary coil and the secondary coil. When a surge voltage isapplied to the secondary coil connected to the pad, the insulating filmmay be deteriorated. A resistance of the normal insulating film beforebeing deteriorated is 1 GΩ or more, and a leakage current is 1 μA orlower. When the high voltage continues to be applied between the primarycoil and the secondary coil in a state where the insulating film isdeteriorated, the resistance value of the insulating film is graduallyreduced, and the leakage current gradually increases. For example, whena voltage of 500 V is applied to the insulating film whose resistancevalue is reduced to 100 kΩ, a current of 500 V/100 kΩ=5 mA flows in theinsulating film, and the amount of heat generation in the insulatingfilm becomes 500 V×5 mA=2.5 W.

When the heat of 2.5 W is generated in a local area within the chip, alatest temperature in the area arrives at 150° C. after 10 ms (time t1).Thereafter, when the resistance value of the insulating film is reducedto 1 kΩ, the current flowing in the insulating film arrives at 0.5 A,and the amount of heat generation of the insulating film arrives at 250W. In this case, the temperature of the chip instantaneously arrives at150° C. or higher, but a current of about 0.5 A is not enough to burnout a peripheral circuit mounted on the chip such as a power circuit.Therefore, the temperature monitoring unit TS1 measures a temperature ofthe semiconductor substrate Sub (time t2), thereby being capable ofdetecting the breakdown of the insulating film.

When a time is further elapsed, the insulation breakdown of theinsulating film grows, and the resistance value of the insulating filmcontinues to be reduced, and a current flowing in the peripheral circuitthrough the insulating film arrives at several tens A to severalhundreds A (time t3). When this large current flows from thesemiconductor device having the on-chip transformer into anotherelectronic circuit mounted on the printed circuit board, there is aconcern about a risk that an electronic circuit that induces burnout orfiring appears.

On the contrary, the insulation breakdown is detected in the temperaturemonitoring unit TS1 at the time t2, and a control such as the cutoff ofa high voltage source is conducted at a time of the detection. As aresult, the system can be stopped safely before the electronic circuitmounted on the printed circuit board is burned out at the time t3. Atime interval between the time t2 and the time t3 is estimated as aboutseveral ms to several tens ms. If the time interval of several ms isprovided from the insulation breakdown detection (time t2), the gatevoltage can be controlled so that the IGBT is turned off in the signaltransmission module MD1 of FIG. 1. Further, if the time interval ofseveral tens ms is provided, a mechanical relay that connects the IGBTand the high voltage source can be turned off.

A transmission time of the heat generated in the insulation breakdownportion, which has been studied by the present inventors, will bedescribed with reference to FIGS. 10A and 10B.

FIG. 10A illustrates a silicon substrate (chip) that is shaped in asquare 3 mm in side and 200 μm in thickness. A weight of the chip is 3mm×3 mm×0.2 mm×2.33 mg/mm³ (density of silicon)=4.2 mg. The specificheat of silicon is 0.7 J/g° C. Therefore, the heat capacity of the chipbecomes 0.7 J/g° C.×4.2 mg=2.94 mJ/° C.

FIG. 10B illustrates a temporal change in a junction temperature Tj ontwo portions of the chip. A line 120 represents a temporal change in thechip temperature when a thermal resistance of the chip is not considered(heat instantaneously diffuses into the chip, and the temperature withinthe chip is uniformly changed regardless of a location). When a heat isproduced in the chip at 10 W at a time 0 ms, and the heat of the chip isnot emitted into air, an overheat time of the chip from a roomtemperature (25° C.) to 150° C. is studied. A temperature rise ratio atthe time of 10 W (500 V, 20 mA) heat generation becomes10(J/s)/2.94(mJ/° C.)=3.4° C./ms. Therefore, a time interval duringwhich the chip is overheated from 25° C. to 150° C. becomes 125(°C.)/3.4(° C./ms)=36 ms (line 120). In fact, because the amount ofradiation into the air is larger as the temperature is higher, thetemperature of the chip is gently raised more as the temperature becomeshigher, and maintained at a temperature at which the amount of heatgeneration is balanced with the amount of radiation.

On the other hand, when the thermal resistance of the chip is taken intoconsideration, a certain amount of time is required for diffusion of theheat into the chip. An inclination of the temperature rise thereforebecomes steep in the vicinity of the insulation breakdown portion (heatsource) where the heat is produced (line 121), and the inclination ofthe temperature rise becomes gentle in a location far from the heatsource (line 122). For example, as indicated by the line 121, when heatof 10 W is produced in the heat source at a time 0 ms, the junctiontemperature Tj arrives at 150° C. in a location close to the heatsource. Also, as indicated by a line 122, a time of about 100 ms isrequired for the junction temperature Tj to arrive at 150° C. in thelocation far from the heat source.

Therefore, in order to promptly detect the rapid temperature rise in theinsulation breakdown portion, it is preferable that the temperaturemonitoring unit TS1 is arranged in the region immediately below or aregion adjacent to the on-chip transformer OCT1 which becomes theinsulation breakdown portion. On the other hand, it is preferable that adistance between the on-chip transformer OCT1 and the heat generationdetermination unit EDET1 is set to be larger than a distance between theon-chip transformer OCT1 and the temperature monitoring unit TS1. Thetemperature rise of the chip is generated later than an insulationbreakdown generation time as the portion is farther than the insulationbreakdown portion which is the high generation source. The temperaturemonitoring unit TS1 is arranged in the vicinity of the heat generationsource, and the heat generation determination unit EDET1 is arranged ata position far from the heat generation source. With this arrangement,the heat generation determination unit EDET1 can normally output theheat generation detection signal Err1 under the condition where thetemperature is maintained at an operation guaranty temperature within adelay time (several tens ms to several hundreds ms) until the junctiontemperature Tj arrives at 150° C.

A description will be given of a mechanism of the abnormal overheatdetection by the temperature monitoring unit TS1 installed in thesemiconductor device LSI1 (without the shield layer), and the heatgeneration determination unit EDET1 according to the first embodimentwith reference to FIGS. 11A and 11B.

FIG. 11A illustrates a connection relationship between an equivalentcircuit of the on-chip transformer OCT1 and the temperature monitoringunit TS1 illustrated in FIG. 6B, and the transmitter circuit TX1 and theheat generation determination unit EDET1 illustrated in FIG. 2. In FIG.11A, it is assumed that the on-chip transformer OCT1 is not equippedwith the shield layers S1 to S3 illustrated in FIG. 6B. As a result,wiring patterns of the line sld1, the line sld2, and the line sld12 forapplying the supply voltage GND1 to those shield layers are deleted.

A drive current of the transmitter circuit TX1 is supplied to both endsof the primary coil L11 of the on-chip transformer OCT1 through the linetx11 and the line tx12. The pad P11 and the pad P12 are connected toboth ends of the secondary coil L12. A pn junction diode that isconnected in parallel between the line sa1 and the line sc1 in the firstsystem, and the pn junction diode that is connected to the line sa2 andthe line sc2 in the second system are further connected in parallel toeach other through the line sa12 and the line sc12. All of the anodesand the cathodes of the pn junction diodes installed in the temperaturemonitoring unit TS1 are connected to the line sa and the line sc,respectively. The temperature monitor signal sa is input to the heatgeneration determination unit EDET1, and the supply voltage GND1 isapplied to the line sc.

FIG. 11B corresponds to a configuration when the shield layer S1 and theshield layer S3 illustrated in FIG. 7B are not provided. When theinsulating film between the primary coil L11 and the secondary coil L12of the on-chip transformer OCT1 is broken down, both of those coils comeclose to a state in which those coils are connected to each other by aninsulating resistor Rins. It is conceivable that a value of theinsulating resistor Rins in a burnout portion is equal to or lower thanseveral kΩ order. The temperature of the semiconductor substrate Sub israised mainly in a region where the pn junction diode Du4 is formed dueto the abnormal heat generation occurring in the burnout portion, andthe forward voltage of the pn junction diode Du4 and the pn junctiondiode arranged in the vicinity of the pn junction diode Du4 are lowered.

When the line sa1 and the line sc1 connected to the anode and thecathode of the pn junction diode Du4 are melted down by the abnormalheat generation of the burnout portion, the rapid temperature rise ofthe semiconductor substrate Sub is detected by the pn junction diodesDu3 to Du1, and the pn junction diode Do arranged adjacent to the linesa1 and the line sc1. Even if a pair of the line sa1 and the line sc1 ispartially melted down, information (a decrease in the forward voltage ofthe diode) indicative of the temperature rise of the semiconductorsubstrate Sub is output to the heat generation determination unit EDET1due to the diode connected in parallel between the line sa1 and the linesc1 arranged between the meltdown portion and the heat generationdetermination unit EDET1. The heat generation determination unit EDET1compares the forward voltage (temperature monitor signal sa) of theplurality of pn junction diodes connected in parallel with a referencevoltage, and outputs a heat generation detection signal Err1 indicativeof the occurrence of the abnormal heat generation.

A description will be given of a mechanism of the abnormality detectionby the temperature monitoring unit TS1 (with the shield layer) installedin the semiconductor device LSI1, and the heat generation determinationunit EDET1 according to the first embodiment with reference to FIGS. 12Aand 12B.

FIG. 12A illustrates a connection relationship between an equivalentcircuit of the on-chip transformer OCT1 (having the shield layers S1 toS3, and the line sld12) and the temperature monitoring unit TS1illustrated in FIG. 6B, and the transmitter circuit TX1 and the heatgeneration determination unit EDET1 illustrated in FIG. 2. Asillustrated in FIG. 12B, when the insulating film is broken down in anupper portion of a region in which the pn junction diode Du4 isarranged, a short-circuiting current flows in the insulating resistorRins between the secondary coil L12 and the primary coil L11, and aninsulating resistor Rsld between the secondary coil L12 and the shieldlayer S1. The short-circuiting that has flown in the shield layer S1flows out to the supply voltage GND1; thereby, it is possible to avoidshort-circuiting between the line sa1 and the line sc1 covered with theshield layer S1, and the secondary coil L12.

Likewise, a short-circuiting current is allowed to flow from thesecondary coil L12 into the supply voltage GND1 through the shield layerS2 or the shield layer S3; thereby it is possible to avoid theshort-circuiting between the line of the first wiring layer and thesecondary coil L12 which are covered with the respective shield layers.This makes it possible to detect the abnormal heat generationattributable to the insulating film breakdown of the on-chip transformerOCT1.

As illustrated in FIG. 11A, the temperature monitoring unit TS1 includesthe pn junction diodes Du1 to Du8 and Dc connected in parallel betweenthe line sa1 and the line sc1 in the first system, and the pn junctiondiode Do connected to the line sa2 and the line sc2 in the secondsystem. All of the pn junction diodes are further connected in parallelthrough the line sa12 and the line sc12. The temperature monitor signalsa which is a voltage across the anode of the pn junction diodesconnected in parallel is input to the heat generation determination unitEDET1. On the other hand, the supply voltage GND1 is applied to thecathode of the pn junction diodes connected in parallel by the line sc.

As described with reference to FIGS. 11A, 11B, 12A, and 12B, when theinsulating film breakdown is generated in the on-chip transformer OCT1,the abnormal heat generation occurs between the first coil and thesecondary coil, and in the periphery of those coils. Therefore, it ispreferable that the pn junction diodes, which are the temperaturedetection elements, are arranged immediately below the formation regionof the on-chip transformer OCT1 (pn junction diodes Du1 to Du8), in thecenter (Dc) thereof, and in the periphery (Do) thereof. Further, becausediameter of the on-chip transformer OCT1 is several hundred micrometers,it is difficult to estimate a portion where the insulation breakdown isgenerated. Also, because heat that propagates through the insulatingfilm (silicon oxide film) of several hundred micrometers from the heatgeneration source, it takes time to detect the abnormal heat generation.It is therefore preferable that multiple temperature detection elementsare arranged.

When multiple pn junction diodes that is the temperature detectionelements is arranged, it is preferable to connect the respective pnjunction diodes in parallel to each other. For example, the pn junctiondiodes Du1 to Du8 and Dc arranged immediately below and in the center ofthe on-chip transformer OCT1 are connected in parallel to each other bythe line sa1 and the line sc1. When the pn junction diodes are connectedin parallel to each other, even if the line sa1 or the line sc1 ismelted down by the short-circuiting current, the temperature monitorsignal sa can be generated by the pn junction diode connected betweenthe meltdown portion and the heat generation determination unit EDET1.

It is preferable that the temperature monitoring unit TS1 is configuredby the temperature detection elements connected to the lines in multiplesystems. The temperature monitoring unit TS1 illustrated in FIGS. 11A,11B, 12A, and 12B have the pn junction diodes connected to the line sa1and the line sc1 in the first system, and the line sa2 and the line sc2in the second system. That the systems of the lines are different fromeach other means that the first wiring layer connected to the anode andthe cathode of the pn junction diodes in a first group, and the firstwiring layer connected to the anode and the cathode of the pn junctiondiodes in a second group are separated from each other in the firstwiring layer. The first wiring layer connected to the anode and thecathode of the pn junction diodes arranged in the vicinity of theportion in which the insulation breakdown is generated is large in arisk of the meltdown caused by the abnormal heat generation. Therefore,in order to prevent the functional deterioration of the temperaturemonitoring unit TS1 caused by the meltdown of the first wiring layer aswell as the loss of the function, it is preferable that the linesconnected to the anodes and the cathodes are distributed into theplurality of systems.

A description will be given of the details of the heat generationdetermination unit EDET1 installed in the semiconductor device LSI1according to the first embodiment with reference to FIG. 13.

FIG. 13 illustrates a detailed circuit diagram of the heat generationdetermination unit EDET1 that outputs the heat generation detectionsignal Err1 on the basis of the temperature monitor signal sa output bythe temperature monitoring unit TS1 illustrated in FIG. 11A.

The heat generation determination unit EDET1 includes a referencevoltage generator circuit REF that generates a reference voltage Vref, acomparator CMP, and a constant current source CC1. The temperaturemonitor signal is input to a negative input terminal of the comparatorCMP, and the reference voltage Vref is input to a positive inputterminal of the comparator CMP.

The comparator CMP outputs the heat generation detection signal Err1 tothe pad 3 on the basis of a comparison result of the temperature monitorsignal sa and the reference voltage Vref. If the voltage of thetemperature monitor signal sa is larger than the reference voltage Vref,the heat generation detection signal Err1 is set to the low level, andif the voltage of the temperature monitor signal sa is smaller than thereference voltage Vref, the heat generation detection signal Err1 is setto the high level. The constant current source CC1 supplies the forwardcurrent to the respective pn junction diodes configuring the temperaturemonitoring unit TS1.

A power supply line VL1 and a power supply line GL1 apply the supplyvoltage VDD1 and the supply voltage GND1 to the heat generationdetermination unit EDET1. On the other hand, a power supply line VL2 anda power supply line GL2 apply the supply voltage VDD1 and the supplyvoltage GND1 to the transmitter circuit TX1. It is preferable that thepower supply line VL1 and the power supply line VL2 are branched fromthe supply voltage VDD1, or branched in a portion close to the supplyvoltage VDD1. The same is applied to the shapes of the power supply lineGL1 and the power supply line GL2.

The heat generation determination unit EDET1 compares the forwardvoltage of the pn junction diode having the negative temperaturecharacteristic (about −2 mV/° C.) with the reference voltage Vref, anddetects the abnormal temperature rise in the region immediately below orin the region adjacent to the on-chip transformer OCT1. It is preferablethat a value of the reference voltage Vref is set to a value that candetect the forward voltage value of the pn junction diodes in thetemperature monitoring unit TS1 at a general temperature 125° C. to 150°C. as a maximum value of the operation guaranty temperature of thesemiconductor device.

When an overheat protection circuit having another TSD (thermalshutdown) function is mounted within the same chip in addition to theheat generation determination unit EDET1, it is preferable that thevalue of the reference voltage Vref set by the heat generationdetermination unit EDET1 is set to a value higher than the referencevoltage set by the overheat protection circuit having another TSDfunction. For example, in the semiconductor device LSI2 illustrated inFIG. 3, the reference voltage set by the heat generation determinationunit EDET2 is set to be higher than the reference voltage set by thetemperature detection unit 30. The respective reference voltages are setas described above with the result that the semiconductor device LSI2normally operates in a guaranty temperature range of the temperaturedetection unit 30.

For example, when the constant current source CC1 supplies a current ofabout 100 μA to 10 pn junction diodes (Du1 to Du8, Dc, and Do)configuring the temperature monitoring unit TS1, the forward voltage ofthe respective diodes becomes about 0.7 V at a room temperature (25°C.). When the temperature of the insulating film is raised from the roomtemperature to 200° C. due to the insulation breakdown of the on-chiptransformer OCT1, the forward voltage of at least one pn junction diodeconfiguring the temperature monitoring unit TS1 is lowered to 450 mV.Therefore, the reference voltage Vref to be applied to the positiveinput terminal of the comparator CMP is set to 0.5 V, as a result ofwhich the heat generation detection signal Err1 changes from the lowlevel to the high level, and the abnormal temperature rise can bedetected.

A description will be given of the configuration of the power supplylines connected to the heat generation determination unit EDET1, thetemperature monitoring unit TS1, and the transmitter circuit TX1installed in the semiconductor device LSI1 according to the firstembodiment with reference to FIGS. 14A and 14B.

FIG. 14A illustrates the configuration of preferable power supply linesfor applying the supply voltage to the respective circuits of the heatgeneration determination unit EDET1, the temperature monitoring unitTS1, the transmitter circuit TX1, and the on-chip transformer OCT1.

The secondary coil L12 of the on-chip transformer OCT1 is connectedbetween the pad P11 and the pad P12. One end of the primary coil L11 isconnected to a drain of a high side p-type transistor M11 in thetransmitter circuit TX1, and the other end of the primary coil L11 isconnected to a drain of a low side n-type transistor M12 in thetransmitter circuit TX1. The supply voltage VDD1 is applied to a sourceof the high side p-type transistor M11 by the power supply line VL2. Thesupply voltage GND1 is applied to the source of the low side n-typetransistor M12 by the power supply line GL2.

When the high voltage of about ±500 V is applied between the primarycoil L11 and the secondary coil L12, and the insulation breakdown isgenerated between both of those coils, the short-circuiting current isgenerated between both of those coils. When the voltage across thesecondary coil L12 is +500 V relative to the voltage across the primarycoil L11, a short-circuiting current Iins1 flows into the power supplyline VL2 (normally 5 V) from the secondary coil L12 through thesecondary coil L12 and a parasitic diode Dp11 between the drain and thesource of the p-type transistor M11. The voltage across the power supplyline VL2 is varied more largely as the position is farther from thesupply voltage VDD1, due to the short-circuiting current Iins1 and aparasitic wiring resistance RVL2 of the power supply line VL2.

Likewise, when the voltage across the secondary coil L12 is −500 Vrelative to the voltage across the primary coil L11, a short-circuitingcurrent Iins2 flows from the power supply line GL2 into the secondarycoil L12 through a parasitic diode Dp12 between the source and the drainof the n-type transistor M12, and the primary coil. The voltage acrossthe power supply line GL2 is varied more largely as the position isfarther from the supply voltage GND1, due to the short-circuitingcurrent Iins2 and a parasitic wiring resistance RGL2 of the power supplyline GL2.

There is a risk that a voltage variation of the power supply line VL2and the power supply line GL2 which is caused by the insulationbreakdown of the on-chip transformer OCT1 adversely influences theoperation of the heat generation determination unit EDET1 that detectsthe insulation breakdown. Under the circumstances, it is preferable thatthe heat generation determination unit EDET1 is arranged in the vicinityof the supply voltage VDD1 and the supply voltage GND1. Thisconfiguration makes it difficult that the supply voltage VDD1 and thesupply voltage GND1 which are applied to the heat generationdetermination unit EDET1 is affected by the voltage variation of theshort-circuiting current generated in the on-chip transformer OCT.

Further, the parasitic resistance of the power supply line that appliesthe supply voltage to the comparator CMP installed in the heatgeneration determination unit EDET1 is smaller than the parasiticresistance of the power supply line that applies the power supply to thetransmitter circuit TX1. When the structures (width, thickness, andmaterial) of the respective power supply lines are identical with eachother, it is preferable that a length lgcmp of the power supply linethat applies the supply voltage GND1 from the supply voltage GND1 to thecomparator CMP is set to be smaller than a length lgtx of the powersupply line that applies the supply voltage GND1 to the transmittercircuit TX1 from the supply voltage GND1 as illustrated in FIG. 14A.More specifically, the length lgtx is a distance between the supplyvoltage GND1 and the source of the low side n-type transistor M12 of thetransmitter circuit TX1.

Likewise, as illustrated in FIG. 14A, it is preferable that the lengthldcmp of the power supply line that applies the supply voltage VDD1 fromthe power supply pad VDD1 to the comparator CMP is set to be smallerthan a length ldtx of the power supply line that applies the supplyvoltage VDD1 to the transmitter circuit TX1 from the supply voltage VDD1as illustrated in FIG. 14A. More specifically, the length ldtx is adistance between the power supply pad VDD1 and the source of the highside p-type transistor M11 of the transmitter circuit TX1. If thestructures of the respective power supply lines are different from eachother, a magnitude relationship of the above lengths is replaced with amagnitude relationship of the parasitic resistance values of therespective power supply lines.

Further, it is preferable that the line sc connected to the cathode ofthe pn junction diodes configuring the temperature monitoring unit TS1is connected not with the power supply line GL2 that applies the supplyvoltage GND1 to the transmitter circuit TX1, but with the power supplyline GL1 that applies the supply voltage GND1 to the heat generationdetermination unit EDET1. As illustrated in FIG. 14B, when the line scof the temperature monitoring unit TS1 is connected to the power supplyline GL2 (for example, neighborhood of the transmitter circuit TX2) inthe vicinity of the on-chip transformer OCT1, the voltage variation ofthe line sc appears as the voltage variation of the line sa, that is,the temperature monitor signal sa. Because the heat generationdetermination unit EDET1 detects the voltage variation of severalhundred millivolts of the temperature monitor signal sa to generate theheat generation detection signal Err1, there is a need to suppress thepower supply variation of the line sc as much as possible.

In the semiconductor device LSI1, the preferable configuration of thepower supply line that applies the supply voltage to the transmittercircuit TX1, the temperature monitoring unit TS1, and the heatgeneration determination unit EDET1, which are connected to the primarycoil L11 of the on-chip transformer OCT1 is described above. It ispreferable to also apply the configuration of the power supply line tothe semiconductor device LSI2 (FIG. 3).

A description will be given of a layout of the temperature monitoringunit TS1 and the temperature monitoring unit TS2 in the semiconductordevice LSI1 and the semiconductor device LSI2 according to the firstembodiment with reference to FIG. 15.

In the semiconductor device LSI1, a distance Loe1 between the on-chiptransformer OCT1 and the heat generation determination unit EDET1 is setto be larger than a distance Los1 between the on-chip transformer OCT1and the temperature monitoring unit TS1. In order to detect the abnormalheat generation caused by the insulating film breakdown of the on-chiptransformer OCT1 as early as possible, the temperature monitoring unitTS1 is arranged in the region immediately below, or in the regionadjacent (the center or the periphery thereof) to the on-chiptransformer OCT1 that is the heat generation source at the time of theinsulation breakdown. On the other hand, in order to reduce the adverseinfluence of the abnormal temperature rise of the chip, which is causedby the short-circuiting current of the on-chip transformer OCT1, theheat generation determination unit EDET1 is arranged distant from theon-chip transformer OCT1 as large as possible. Further, in order tosuppress the influence of the noises generated in the power supply line,which is attributable to the short-circuiting current, the heatgeneration determination unit EDET1 is arranged close to the supplyvoltage VDD1 and a power supply pad GNG1.

In the semiconductor device LS21, a distance Loe2 between the on-chiptransformer OCT2 and the heat generation determination unit EDET2 is setto be larger than a distance Lost between the on-chip transformer OCT2and the temperature monitoring unit TS2. In order to detect the abnormalheat generation caused by the insulating film breakdown of the on-chiptransformer OCT2 as early as possible, the temperature monitoring unitTS2 is arranged in the region immediately below, or in the regionadjacent (the center or the periphery thereof) to the on-chiptransformer OCT2 that is the heat generation source at the time of theinsulation breakdown. On the other hand, in order to reduce the adverseinfluence of the abnormal temperature rise of the chip, which is causedby the short-circuiting current of the on-chip transformer OCT2, theheat generation determination unit EDET2 is arranged distant from theon-chip transformer OCT2 as large as possible. Further, in order tosuppress the influence of the noises generated in the power supply line,which is attributable to the short-circuiting current, the heatgeneration determination unit EDET2 is arranged close to the powersupply pad VDD2 and a power supply pad GNG2.

A specific example of the reference voltage generator circuit REFprovided in the heat generation determination unit EDET1 installed inthe semiconductor device LSI1 according to the first embodiment will bedescribed with reference to FIGS. 16A and 16B.

FIG. 16A illustrates an example in which a bandgap reference circuit BGRis applied as the reference voltage generator circuit REF. The referencevoltage Vref not depending on the temperature of the chip, which isgenerated by the bandgap reference circuit BGR, is applied to thepositive input terminal of the comparator CMP. The comparator CMPcompares a fixed voltage corresponding to an absolute temperature (forexample, 175° C.) with the temperature monitor signal sa output by thetemperature monitoring unit TS1 at the time of supplying a forwardcurrent I1 of the constant current source CC1, and outputs the heatgeneration detection signal Err1 of the high level when a junctiontemperature of the pn junction diode arranged in the region immediatelybelow or in the region adjacent to the on-chip transformer OCT1 exceeds175° C. FIGS. 16A and 16B illustrate a circuit diagram in which theon-chip transformer OCT1 is schematically illustrated as a coilexpressed in a perspective view.

FIG. 16B illustrates an example in which the reference voltage generatorcircuit REF is configured by a reference constant current source CCRthat generates a forward current I1-α and a reference temperaturedetection element TSR to which the forward current I1-α is supplied. Theforward voltage of the reference temperature detection element TSR isapplied to the positive input terminal of the comparator CMP. Thetemperature monitor signal sa output by the temperature monitoring unitTS1 at the time of supplying the forward current I1 of the constantcurrent source CC1 is supplied to the negative input terminal. Thecomparator CMP compares the forward voltage with the temperature monitorsignal sa to generate the heat generation detection signal Err1.

The reference temperature detection element TSR is arranged at adistance from the layout region of the temperature monitoring unit TS1within the chip. That is, a distance between the on-chip transformerOCT1 and the reference temperature detection element TSR is set to belarger than a distance between the on-chip transformer OCT1 which is theabnormal heat generation source, and the temperature monitoring unitTS1. For example, the reference temperature detection element TSR may bearranged adjacent to the comparator CMP. When a temperature detected bythe temperature monitoring unit TS1 becomes higher than a temperaturedetected by the reference temperature detection element TSR by, forexample, 50° C. or higher, the comparator CMP outputs the heatgeneration detection signal Err1 of the high level. Since thetemperature monitor signal sa is compared with the forward voltage ofthe reference temperature detection element TSR, the voltage generatorcircuit such as the bandgap reference circuit become unnecessary,resulting in advantages that the circuit is simplified, and the chiparea is reduced.

When the forward current to be supplied to the reference temperaturedetection element TSR is made smaller than the value of the forwardcurrent I1 to be supplied to the temperature monitoring unit TS1 by a asI1-α, a detection threshold value of the comparator CMP corresponding tothe detected temperature difference is set. Alternatively, it ispossible that values of both the forward currents are made identicalwith each other, and an offset is set in the input threshold value ofthe comparator CMP to adjust the detected temperature by the temperaturemonitoring unit TS1 and the reference temperature detection element TSR.

Another example of the reference voltage generator circuit provided inthe heat generation determination unit EDET1 installed in thesemiconductor device LSI1 according to the first embodiment will bedescribed with reference to FIGS. 17A and 17B.

FIG. 17A illustrates a configuration of a heat generation determinationunit EDET11. The heat generation determination unit EDET11 includes acomparator CMP1, a comparator CMP2, the constant current source CC1, andan OR circuit G1. The temperature monitor signal sa output by thetemperature monitoring unit TS1 to which the forward current is suppliedfrom the constant current source CC1 is supplied to a negative inputterminal of the comparator CMP1 and a positive input terminal of thecomparator CMP2. A reference voltage Vref1 (0.5 V), which is assumed asthe forward voltage output when the temperature monitoring unit TS1 is150° C., is applied to a positive input terminal of the comparator CMP1.A reference voltage Vref2 (1.0 V), which is assumed as the forwardvoltage output when the temperature monitoring unit TS1 is −50° C., isapplied to a negative input terminal of the comparator CMP2.

If the value of the temperature monitor signal sa to be applied to thenegative input terminal is smaller than the reference voltage Vref1 tobe applied to the positive input terminal, the comparator CMP1 outputsthe high level. If the temperature monitor signal sa to be applied tothe positive input terminal is larger than the reference voltage Vref2to be applied to the negative input terminal, the comparator CMP2outputs the high level. The OR circuit G1 outputs the heat generationdetection signal Err1 of the high level when any one of the comparatorCMP1 and the comparator CMP2 becomes the high level.

That is, the heat generation determination unit EDET11 detects that thetemperature detected by the temperature monitoring unit TS1 fallsoutside a temperature range of −50° C. to +150° C. assumed as the usageenvironment of the semiconductor device. If the chip temperature fallsoutside +150° C., the heat generation detection signal Err1 is set tothe high level, and the insulation breakdown of the on-chip transformerOCT1 is detected.

FIG. 17B is a diagram illustrating the operation of the heat generationdetermination unit EDET11 when the line sa connected with thetemperature monitoring unit TS1 is melted down. The temperaturemonitoring unit TS1 is arranged immediately below or in the vicinity ofthe on-chip transformer OCT1. For that reason, the line sa thattransmits the measured output of the temperature monitoring unit TS1 tothe heat generation determination unit EDET11 may be melted down by theabnormal heat generation occurring in the insulation breakdown of theon-chip transformer OCT1. In this case, although the temperature monitorsignal sa is not input to the heat generation determination unit EDET11,because a load current of the constant current source CC1 becomessubstantially null, the output of the constant current source CC1 israised to the supply voltage VDD1 (5 V). The raised output voltage ofthe constant current source CC1 is compared with the reference voltageVref2 (1.0 V) of the comparator CMP2, and the comparator CMP2 outputsthe high level. As a result, the heat generation detection signal Err1becomes the high level, and the insulation breakdown of the on-chiptransformer OCT1 is detected.

A description will be given of a variety of configuration examples ofthe temperature monitoring unit TS1 according to the respectiveembodiments with reference to FIGS. 18A to 18D.

FIG. 18A illustrates a pn junction diode D described as a specificexample of the temperature monitoring unit TS1 according to the firstembodiment. A given constant current is supplied to the pn junctiondiode D in the forward direction, and the forward voltage of the anodeto the cathode connected with the supply voltage GND1 is compared withthe reference voltage Vref by the comparator CMP to output the heatgeneration detection signal Err1.

FIG. 18B illustrates a temperature monitoring unit that supplies a givenconstant current between a base and an emitter of a diode-connectedbipolar transistor Q in the forward direction, and detects a chiptemperature by the forward voltage of the base to the emitter to whichthe supply voltage GND1 is applied. FIG. 18C illustrates a temperaturemonitoring unit that short-circuits between a gate and a drain of adiode-connected MOS transistor M, and detects the chip temperature bythe gate voltage to the source to which the supply voltage GND1 isapplied. FIG. 18D is a temperature monitoring unit that supplies a givenconstant current to a resistor having a temperature dependency, anddetects the chip temperature by a voltage generated between both ends ofthe resistor. As a resistor whose resistance value has a temperaturecoefficient, a polycrystal silicon resistor, a diffused resistor, a wellresistor, and a metal resistor can be applied.

Other modifications of the heat generation determination unit accordingto the respective embodiments will be described with reference to FIGS.19A to 19C.

FIG. 19A illustrates a temperature monitoring unit TS11 that applies thesupply voltage VDD1 to the cathode of a diode D11, and a heat generationdetermination unit EDET11 a including a transistor M, a capacitor Cap,and the comparator CMP. An anode of the diode D11 is connected to adrain of the transistor M, the supply voltage GND1 is applied to asource of the transistor M, and a signal CLR is supplied to a gate ofthe transistor M. A voltage across the drain of the transistor M isapplied to the positive input terminal of the comparator CMP as a signalINTEG. The reference voltage Vref is applied to the negative inputterminal of the comparator CMP. The capacitor Cap is connected betweenthe positive input terminal of the comparator CMP and the supply voltageGND1.

FIG. 19B illustrates a method of generating the heat generationdetection signal Err1 by the temperature monitoring unit TS11 and theheat generation determination unit EDET11 a illustrated in FIG. 19A.Before a time t0 at which the temperature monitoring unit TS1 starts thetemperature measurement, the transistor M having the gate to which thesignal CLR of the high level (VDD1) has been supplied maintains thesupply voltage GND1 between both terminals of the capacitor Cap, anddischarges the stored charge. When the signal CLR is set to the lowlevel at the time t0, the capacitor Cap is charged with the leakagecurrent of the inversely biased diode D11, and a voltage of the signalINTEG starts to rise.

When the voltage of the signal INTEG exceeds the reference voltage Vref,the comparator CMP outputs the heat generation detection signal Err1 ofthe high level. The leakage current of the diode D11 increases more as apn junction temperature of the diode D11 is raised more. Therefore, timeintervals since the time t0 at which the logic level of the signal CLRhas been changed till the times t1/t2/t3 at which the logic level of theheat generation detection signal Err1 is changed from the low level tothe high level are measured, thereby being capable of detecting theinsulation breakdown of the on-chip transformer OCT1.

FIG. 19C illustrates the temperature monitoring unit TS11 that appliesthe supply voltage VDD1 to the cathode of the diode D11, and the heatgeneration determination unit having an oscillator circuit in whichmultiple inverters 11 c is connected in cascade. The respectiveinverters 11 c connected in cascade are applied with the supply voltagefrom the anode of the diode D11. The voltage across the anode of thediode D11 is raised more as the pn junction temperature rises.Therefore, the number of oscillations in the oscillator circuitconfigured by the inverters 11 c is measured by a counter not shown fora given time, and if the count value of the number of oscillationsexceeds a given value, the logic level of the heat generation detectionsignal Err1 is inverted, thereby being capable of detecting theinsulation breakdown of the on-chip transformer OCT1.

A configuration of the temperature monitoring unit TS11 which is amodification of the temperature monitoring unit TS1 installed in thesemiconductor device LSI1 according to the first embodiment will bedescribed with reference to FIGS. 20A and 20B.

FIG. 20A is a layout plan view of the temperature monitoring unit TS11.The temperature monitoring unit TS11 includes multiple pn junctiondiodes (temperature detection elements) formed on the semiconductorsubstrate, and each of the pn junction diodes has an anode A and acathode C. The pn junction diodes Du1 to Du8 are arranged immediatelybelow the on-chip transformer OCT1, the pn junction diode Dc is arrangedin the center of the on-chip transformer OCT1, and pn junction diodesDo1 and Do2 are arranged in the outer periphery of the on-chiptransformer OCT1.

The anodes and the cathodes of the pn junction diodes Du1 to Du3 areconnected to the line sa1 and the line sc1 in the first system,respectively. The anodes of the pn junction diodes Du, Dc, and Du8 areconnected to the line sat in the second system, and the cathodes ofthose diodes are connected to the line sc2 in the second system. Theanodes and the cathodes of the pn junction diodes Du5 to Du7 areconnected to the line sa3 in the third system, and the line sc3 in thethird system, respectively. The anodes of the pn junction diodes Do1 andDo2 are connected to a line sa4 in a fourth system, and the cathodes ofthose diodes are connected to a line sc4 in the fourth system.

FIG. 20B is an equivalent circuit diagram of the temperature monitoringunit TS11 illustrated in FIG. 20A. The above diodes are connected inparallel between the respective lines of the first to fourth systems.

A layout relationship between the temperature monitoring unit TS11 andthe on-chip transformer OCT1 installed in the semiconductor device LSI1according to the first embodiment will be described with reference toFIGS. 21A and 21B.

FIG. 21A is a plan view illustrating a configuration in which the firstwiring layer overlaps with the second wiring layer forming the primarycoil L11 of the on-chip transformer OCT1. The shield layer S1 and theshield layer S3, which are formed of the second wiring layer, are eachconnected to the line sld12 formed of the first wiring layer through thevia hole v12, and the shield layer S2 formed of the second wiring layeris connected to a line sld21 formed of the first wiring layer throughthe via hole v12. The line sld12 and the line sld21 are connected to aline sld22 formed of the second wiring layer through the via hole v12.The line sa1, a line sa3, and a line sa4, which are formed of the firstwiring layer, are connected to a line sa22 formed of the second wiringlayer through the via hole v12. The line sc1, the line sc2, the linesc3, and the line sc4, which are formed of the first wiring layer, areconnected to a line sc22 which is formed of the second wiring layerthrough the via hole v12.

FIG. 21B illustrates a relationship between the respective pn junctiondiodes configuring the temperature monitoring unit TS11, and the shieldlayers S1 to S3. The shield layer S1 is formed to cover the diode Dcformed in the center of the on-chip transformer OCT1, and the line sa2and the line sc2 which are connected to the diode Dc. The shield layerS2 is formed to cover the diodes Do1 and Do2 which are arranged in theouter periphery of the primary coil L11, and the line sa4 and the linesc4 which are connected to the primary coil L11. The shield layer S3 isformed to cover the line sa2 and the line sa2 in the vicinity of theon-chip transformer OCT1. The shield layers S1 to S3 are applied withthe supply voltage GND1.

The temperature monitoring unit TS11 has a configuration in which therespective diodes arranged in the region immediately below, in thecenter of, and in the outer periphery of the on-chip transformer OCT1are divided into four wiring systems (lines sa1/sc1, lines sa2/sc2,lines sa3/sc3, lines sa4/sc4), and connected in parallel to each other.With an increase in the number of wiring systems in which the diodes areconnected in parallel to each other, even if any wiring system is melteddown, the temperature monitoring unit TS11 can hold a function ofdetecting the abnormal temperature rise.

A system configuration formed of the signal transmission modules MD1having the semiconductor device LSI1 and the semiconductor device LSI2according to the first embodiment will be described with reference toFIG. 22.

FIG. 22 illustrates a system example in which the signal transmissionmodules MD1 are applied to the IGBT driver. Transistors QH1, QH2, andQH3 of the high side, and transistors QL1, QL2, and QL3 of the low sideare connected in cascade to each other through connection points U, V,and W, respectively, to form a three-phase inverter. The respectivetransistors are each formed of an IGBT, the collectors of the high sidetransistors are applied with a high DC voltage of 500 V, and theemitters of the low side transistors are applied with a groundpotential. An AC current of three phases is supplied to a motor M fromthe connection points U, V, and W.

The bases of the respective transistors are supplied with the drivesignal IGDry output by the respective signal transmission modules MD1.Each of the signal transmission modules MD1 generates the drive signalIGDry on the basis of the signal In1 output by a microcomputer MCU.Further, the signal transmission module MD1 outputs the output signalRox1 and the heat generation detection signal Err1 to the microcomputerMCU. The microcomputer MCU controls the conductivity of a mechanicalrelay RLY and a transistor QSW which is an IGBT, on the basis of theoutput signal Rox1 and the heat generation detection signal Err1.

A system control method by the signal transmission module MD1 at thetime of generating the insulation breakdown according to the firstembodiment will be described with reference to FIG. 23.

FIG. 23 illustrates a configuration of the semiconductor device LSI1 andthe semiconductor device LSI2 mounted on the signal transmission moduleMD1 according to the first embodiment. The configuration and theoperation of the semiconductor device LSI1 and the semiconductor deviceLSI2 in FIG. 23 are identical with the configuration and the operationillustrated in FIGS. 2 and 3, respectively. The semiconductor deviceLSI1 is a primary side signal transmission chip that directly transmitsand receives a signal with respect to the microcomputer MCU. Thesemiconductor device LSI2 is a secondary side signal transmission chipthat controls the switching operation of the IGBT to which the high DCvoltage is applied.

The system protection operation when the insulation breakdown of theon-chip transformer OCT1 is generated in the primary side signaltransmission chip (LSI1) will be described.

When the chip temperature is raised by the insulation breakdown of theon-chip transformer OCT1 mounted on the semiconductor device LSI1, theheat generation determination unit EDET1 outputs the heat generationdetection signal Err1 to the microcomputer MCU. Upon receiving the heatgeneration detection signal Err1, the microcomputer MCU switches thetransistor QSW and the mechanical relay RLY from a conductive state to anonconductive state, and cuts off the high DC voltage to be applied tothe inverter.

When the high DC voltage to be applied to the inverter is cut off, thesupply voltage VDD2 to be applied to the secondary side signaltransmission chip (LSI2) is rapidly lowered, and a voltage across thesecondary coil (L12) of the on-chip transformer OCT1 is also rapidlylowered. As a result, the short-circuiting current between the secondarycoil (L12) and the primary coil (L11) of the on-chip transformer OCT1 isalso rapidly decreased. Also, the signal transmission module MD1 as wellas other electronic components (microcomputer MCU, etc.) mounted on thesame printed circuit board as that of the signal transmission module MD1can be prevented from being burned out, and fired.

Also, when the microcomputer MCU receives the heat generation detectionsignal Err1 from the semiconductor device LSI1, the microcomputer MCUinstructs the signal transmission module MD1 that drives the respectivetransistors QH1 to QH3 to render the transistors QH1 to QH3 of the highside nonconductive. When the transistors QH1 to QH3 of the high side arerendered conductive, a neutral potential (potential (supply voltageGND2) of the connection points U, V, and W) of a half bridge becomesequal to the ground potential of the low side, and a potentialdifference to be applied to an insulating portion between the primarycoil and the secondary coil of the primary side signal transmission chipbecomes null. In this situation, in order to lower the neutral potentialof the half bridge, the transistors QL1 to QL3 of the low side may beset in the conductive state.

When the temperature monitoring unit TS1 of the semiconductor deviceLSI1 detects the abnormal overheat of the on-chip transformer OCT1, thetransistors QH1 to QH3 of the high side may be set in the nonconductivestate not through the microcomputer MCU, but directly by the signaltransmission module MD1.

In the signal transmission module MD1 illustrated in FIG. 23, when thetemperature monitoring unit TS1 detects the abnormal overheat, the heatgeneration determination unit EDET1 outputs the heat generationdetection signal Err1 to the control circuit CTL1 in addition to theheat generation detection signal Err1 transmission to the microcomputerMCU described above. The control circuit CTL1 transmits a given signalto the receiver circuit RX2 of the semiconductor device LSI2 through thetransmitter circuit TX1 and the on-chip transformer OCT1.

The driver circuit DRV of the semiconductor device LSI2 outputs thedrive signal IGDry that renders the IGBT nonconductive on the basis ofthe given signal. The generation of the drive signal IGDry by the IGBTdriver circuit DRV from the detection of the abnormal overheat by thetemperature monitoring unit TS1 is conducted by hardware (electroniccircuit) installed in the signal transmission module MD1. Therefore, theIGBT can be rendered nonconductive before the on-chip transformer OCT1is burned out, and the function is lost from the abnormal overheatgeneration.

Subsequently, a description will be given of the system protectionoperation when the insulation breakdown of the on-chip transformer OCT2is generated in the secondary side signal transmission chip (LSI2). Inthe signal transmission module MD1 illustrated in FIG. 23, when thetemperature monitoring unit TS2 detects the abnormality overheat of theon-chip transformer OCT2, the heat generation determination unit EDET2outputs the heat generation detection signal Err2 to the control circuitCTL2. In response to the heat generation detection signal Err2, thecontrol circuit CTL2 changes the output signal Ct2 to be output to theIGBT driver circuit DRV from the low level to the high level, andoutputs the drive signal IGDry that renders the IGBT nonconductive. Onthe basis of the drive signal IGDrv, the IGBT becomes in thenonconductive state to protect the system.

The generation of the drive signal IGDry by the IGBT driver circuit DRVfrom the detection of the abnormal overheat by the temperaturemonitoring unit TS2 is conducted by only a hardware installed in thesecondary side signal transmission chip regardless of the instructionfrom the microcomputer MCU. Therefore, the IGBT can be renderednonconductive before the on-chip transformer OCT2 is burned out, and thefunction is lost from the abnormal overheat generation.

Another layout example of the temperature monitoring unit TS1 installedin the semiconductor device LSI1 according to the first embodiment willbe described with reference to FIG. 24.

As described above, it is preferable that the temperature monitoringunit TS1 installed in the semiconductor device LSI1 is arranged in theregion immediately below or in the region adjacent to the on-chiptransformer OCT1. However, the layout place of the temperature detectionelements (pn junction diodes, etc.) configuring the temperaturemonitoring unit TS1 is not limited to the above places. The temperaturemonitoring unit TS11 illustrated in FIG. 24 is arranged in adjacent to atransmission driver circuit provided in the transmitter circuit TX1installed in the semiconductor device LSI1, and detects the abnormaloverheat attributable to the insulation breakdown of the on-chiptransformer OCT1. FIG. 24 illustrates a circuit diagram, but the on-chiptransformer OCT1 is schematically illustrated as a coil expressed in aperspective view.

Referring to FIG. 24, the transmission driver circuit includes thep-type transistor M11 having a source applied with the supply voltageVDD1 and a drain connected with the line tx11, the n-type transistor M12having a drain connected with the line tx11 and a source applied withthe supply voltage GND1, a p-type transistor M13 having a source appliedwith the supply voltage VDD1 and a drain connected with the line tx12,and an n-type transistor M14 having a drain connected with the line tx12and a source applied with the supply voltage GND1. The respective gatevoltages of the p-type transistor M11 and the n-type transistor M14, andthe p-type transistor M13 and the n-type transistor M12 are controlledby a pre-driver circuit not shown, so as to allow respective reversedrive currents to flow into the primary coil L11 through the line tx11and the line tx12.

When the short-circuiting current is generated between the primary coilL11 and the secondary coil L12 of the on-chip transformer OCT1 due tothe insulation breakdown, the short-circuiting flows into the powersupply line VDD1 or the power supply lines GND1 from the secondary coilL12 through the above transistor or the parasitic diode (not shown) ofthe transmission driver circuit. The temperature rise of thetransmission driver circuit due to the short-circuiting current isdetected by the temperature monitoring unit TS11 configured by thediodes D11 to D14 arranged in the vicinity of the respective,transistors M11 to M14 configuring the transmission driver circuit,respectively.

The nodes of the diodes D11 and D13 are connected to the line sa1, andthe anodes of the diodes D12 and D14 are connected to the line sa2. Bothof the line sa1 and the line sa2 are connected to the heat generationdetermination unit EDET1. The cathodes of the diode D11 and the diodeD13 are connected to the line sc1, and the cathodes of the diode D12 andthe diode D14 are connected to the line sc2. The line sc1 and the linesc2 are applied with the supply voltage GND1. The diode D11 and thediode D13 are connected in parallel between the line sa1 and the linesc1 in the first system, and the diode D12 and the diode D14 areconnected in parallel between the line sa2 and the line sc2 in thesecond system. The line is separated into the two systems, to therebyimprove the reliability of the temperature monitoring unit TS11.

Another layout example of the temperature monitoring unit TS21 installedin a semiconductor device LSI2 according to the first embodiment will bedescribed with reference to FIG. 25.

The layout of the temperature monitoring unit is not limited to the chipside on which the on-chip transformer is formed, but may be arranged onthe chip side that receives the signal from the chip on which theon-chip transformer is formed. A temperature monitoring unit TS21illustrated in FIG. 1 s another layout example of the temperaturemonitoring unit TS1. The temperature monitoring unit TS21 is arranged inadjacent to an electrostatic protection element of the receiver circuitRX2 installed in the semiconductor device LSI2, and detects the abnormaloverheat attributable to the insulation breakdown of the on-chiptransformer OCT1. FIG. 25 illustrates a circuit diagram, but the on-chiptransformer OCT1 is schematically illustrated as a coil expressed in theperspective view.

In the semiconductor device LSI1, the primary coil L11 of the on-chiptransformer OCT1 is applied with a drive current output by thetransmitter circuit TX1. One end of the secondary coil L12 is connectedto the pad P11, and the other end of the secondary coil L12 is connectedto the pad P12. The pad P11 and the pad P12 of the semiconductor deviceLSI1 are connected to the pad P21 and the pad P22 formed on thesemiconductor device LSI2 by the bonding wires 1, respectively.

In the semiconductor device LSI2, the pad P21 is applied with the supplyvoltage VDD2 through a resistor Rr and a power supply line 25. Thesupply voltage VDD2 is applied to the pad P11 connected with one of thesecondary coil L12 as a reference voltage of the on-chip transformerOCT1. The resistor Rr is not always required for applying the referencevoltage to the secondary coil L12, but is provided to detect a currentbetween the pad P21 and the power supply line VDD2. The resistor Rr isformed of a polycrystal silicon resistor or a diffused resistor. A diodeD23 provided in the temperature monitoring unit TS21 is arrangedadjacent to the resistor Rr.

A voltage generated in the other end of the secondary coil L12 isapplied to the pad P22, and the voltage is applied to the input terminalof the receiver circuit RX2. An electrostatic protection element D1 eand an electrostatic protection element D2 e are connected between thatinput terminal, and the power supply line GND2 and the power supply lineVDD2, respectively. Diodes D21 and D22 configuring the temperaturemonitoring unit TS21 are arranged in the vicinity of the electrostaticprotection element D1 e and the electrostatic protection element D2 e,respectively.

The short-circuiting current generated in the on-chip transformer OCT1of the semiconductor device LSI1 flows between the pad P11 and the padP21, and between the pad P12 and the pad P22 through the bonding wires1. The short-circuiting current that inflows and outflows through thepad P21 flows into the power supply line VDD2 through the resistor Rrand the power supply line 25, and the temperature of the resistor Rr andthe semiconductor substrate close to the resistor Rr start to rapidlyrise. The short-circuiting current that inflows and outflows through thepad P22 flows into the power supply line GND2 and the power supply lineVDD2 through the electrostatic protection element D1 e and theelectrostatic protection element D2 e, respectively, and the temperatureof the respective electrostatic protection elements and thesemiconductor substrate close to those electrostatic protection elementsstarts to rapidly rise.

The diodes D21, D22, and D23 configuring the temperature monitoring unitTS21 lower the forward voltage with a rise in the temperature of theelectrostatic protection element D1 e, the electrostatic protectionelement D2 e, and the resistor Rr. The anode voltages across the diodesD21, D22, and D23, which are connected in parallel to each other, areinput to the heat generation determination unit EDET2. If the forwardvoltage is abnormally lowered in at least any one of the diodes D21,D22, and D23, the heat generation determination unit EDET2 outputs theheat generation detection signal Err2.

The temperature monitoring unit is not always arranged in the regionimmediately below or in the region adjacent to the on-chip transformer,but may be arranged in the vicinity of a region in which a circuit intowhich the short-circuiting current generated in the on-chip transformercan flow is formed. As a result, the chip in which the on-chiptransformer is formed, and the chip in which the temperature monitoringunit is formed can be set, separately, to improve the degree of freedomof design of the signal transmission module.

Second Embodiment

A configuration of a signal transmission module MD2 having asemiconductor device LSI12 and a semiconductor device LSI22 according toa second embodiment will be described with reference to FIG. 26.

The semiconductor devices LSIi (i=1, 2) according to the firstembodiment has a transmitter circuit TXi and an on-chip transformer OCTiwhereas the semiconductor device LSIj2 (j=1, 2) according to the secondembodiment has a receiver circuit RXj and an on-chip transformer OCTj.The circuits and so on installed in the semiconductor device LSI12 andthe semiconductor device LSI22 according to the second embodiment havethe same configuration and function as those denoted by the samereference numerals or symbols with those in the semiconductor deviceLSI1 and the semiconductor device LSI2 according to the firstembodiment.

The transmitter circuit TX1 installed in the semiconductor device LSI12drives the on-chip transformer OCT2 installed in the semiconductordevice LSI22 through the pads 3 and the bonding wires 1. Likewise, thetransmitter circuit TX2 installed in the semiconductor device LSI22drives the on-chip transformer OCT1 installed in the semiconductordevice LSI12.

In the semiconductor device LSI12, the temperature monitoring unit TS1is arranged in the vicinity of the on-chip transformer OCT1, and theheat generation determination unit EDET1 is arranged in the vicinity ofthe power supply pad VDD1 and the power supply pad GND1. The forwardvoltage between the anode and the cathode of the diode provided in thetemperature monitoring unit TS1 is input to the heat generationdetermination unit EDET1 through the line sa and the line sc. A distanceLoe12 between the on-chip transformer OCT1 and the heat generationdetermination unit EDET1 is set to be larger than a distance Los12between the on-chip transformer OCT1 and the temperature monitoring unitTS1.

In the semiconductor device LSI22, the temperature monitoring unit TS2is arranged in the vicinity of the on-chip transformer OCT2, and theheat generation determination unit EDET2 is arranged in the vicinity ofthe power supply pad VDD2, and the power supply pad GND2. The forwardvoltage between the anode and the cathode of the diode provided in thetemperature monitoring unit TS2 is input to the heat generationdetermination unit EDET2 through the line sa and the line sc. A distanceLoe22 between the on-chip transformer OCT2 and the heat generationdetermination unit EDET2 is set to be larger than a distance Los22between the on-chip transformer OCT2 and the temperature monitoring unitTS2.

The on-chip transformer is not always formed in the chip having thetransmitter circuit, but may be formed in a chip having a receivercircuit. A range of choices of the chip forming the on-chip transformeris widened to increase the degree of freedom of design of other circuitsmounted on the chip. Also, like the heat generation determination unitEDET1 and the transmitter circuit TX1 in FIG. 13, it is preferable thatthe supply voltage VDD2 is applied to each of the heat generationdetermination unit EDET2 and the receiver circuit RX2 by the powersupply lines branched from the power supply pad VDD2. With thisconfiguration, an adverse influence of the noise of the power supplylines on the heat generation determination unit EDET2 is reduced. Thesame is applied to the power supply lines for applying the supplyvoltage GND2 to the heat generation determination unit EDET2 and thereceiver circuit RX2.

Third Embodiment

A configuration of a signal transmission module MD3 having asemiconductor device LSI13 and a semiconductor device LSI23 according toa third embodiment will be described with reference to FIGS. 27A and27B.

FIG. 27A is a plan view schematically illustrating a circuit patternwhen the circuit pattern formed on a chip top of the semiconductordevice LSI13 is viewed from the chip top, and a circuit pattern when thecircuit pattern formed on a chip top of the semiconductor device LSI23is viewed through a chip backside thereof. The chip top means one of twoopposed surfaces of the semiconductor substrate on which a circuitelement such as a transistor is formed. A signal transmission betweenthe semiconductor device LSI13 and the semiconductor device LSI23 isconducted through a transformer formed by allowing the chip tops to faceeach other. In the third embodiment, a transformer formed by opposed twochips is also called “on-chip transformer”.

The semiconductor device LSI13 is formed with a primary side coil L13 ofan on-chip transformer OCT3 covered with an insulating film, and asecondary side coil L24 of an on-chip transformer OCT4. The primary sidecoil L13 is driven by the transmitter circuit TX1, an electromotiveforce caused by electromotive induction generated in the secondary sidecoil L24 is input to the receiver circuit RX1. A temperature monitoringunit TS13 and a temperature monitoring unit TS14 are arranged in thevicinity of the primary side coil L13 and the secondary side coil L24,for example, in the center thereof, respectively. The forward voltagebetween the anode and the cathode of the diode provided in each of thetemperature monitoring unit TS13 and the temperature monitoring unitTS14 is input to the heat generation determination unit EDET1 throughthe line sa1 and the line sc1.

The heat generation determination unit EDET1 is arranged in the vicinityof the supply voltage VDD1 and the supply voltage GND1, and outputs theheat generation detection signal Err1 to the pads 3. A distance betweenthe primary side coil L13 and the heat generation determination unitEDET1 is set to be larger than a distance between the primary side coilL13 and the temperature monitoring unit TS13. A distance between thesecondary side coil L24 and the heat generation determination unit EDET1is set to be larger than a distance between the secondary side coil L24and the temperature monitoring unit TS14.

The semiconductor device LSI23 is formed with a secondary coil L23 ofthe on-chip transformer OCT3 covered with an insulating film, and aprimary coil L14 of the on-chip transformer OCT4. The electromotiveforce caused by the electromagnetic induction generated in the secondarycoil L23 is input to the receiver circuit RX2, and the primary coil L14is driven by the transmitter circuit TX2. A temperature monitoring unitTS23 and a temperature monitoring unit TS24 are arranged in the vicinityof the secondary coil L23 and the primary coil L14, for example, in thecenter thereof, respectively. The forward voltage between the anode andthe cathode of the diode provided in each of the temperature monitoringunit TS23 and the temperature monitoring unit TS24 is input to the heatgeneration determination unit EDET2 through the line sa2 and the linesc2.

The heat generation determination unit EDET2 is arranged in the vicinityof the pad VDD2 and the pad GND2. A distance between the secondary coilL23 and the heat generation determination unit EDET2 is set to be largerthan a distance between the secondary coil L23 and the temperaturemonitoring unit TS23. A distance between the primary coil L14 and theheat generation determination unit EDET2 is set to be larger than adistance between the primary coil L14 and the temperature monitoringunit TS24.

FIG. 27B is a cross-sectional view of two chips which face each other sothat a Y-axis (Y13-Y13) set in the semiconductor device LSI13 matches aY-axis (Y23-Y23) set in the semiconductor device LSI23 illustrated inFIG. 27A, taken along an X-axis (X-X′). In the third embodiment, acenter of the primary side coil L13 and the secondary side coil L24 inthe semiconductor device LSI13 is put on the same Y-axis (Y13-Y13), anda center of the secondary coil L23 and the primary coil L14 in thesemiconductor device LSI23 is put on the same Y-axis (Y23-Y23).

Further, a center interval between the primary side coil L13 and thesecondary side coil L24 in the semiconductor device LSI13 is set to beequal to a center interval between the secondary coil L23 and theprimary coil L14 in the semiconductor device LSI23. The layout of theprimary coil and the secondary coil in both of those chips is notlimited to the above-mentioned layout, but can be appropriately changedso that the on-chip transformer is formed when both of those chips isarranged to face each other.

The top of a semiconductor substrate Sub1 of the semiconductor deviceLSI13 is formed with a diode provided in the temperature monitoring unitTS13 arranged in the center of the primary side coil L13. The primaryside coil L13 is embedded in an insulating film formed on thesemiconductor substrate Sub1. A semiconductor substrate Sub2 of thesemiconductor device LSI23 is formed with a diode provided in thetemperature monitoring unit TS23 arranged in the center of the secondarycoil L23. The secondary side coil L23 is embedded in an insulating filmformed on the semiconductor substrate Sub2. The semiconductor deviceLSI13 and the semiconductor device LSI23 are arranged to face each otherso that the respective centers of the primary side coil L13 and thesecondary coil L23 match each other. The primary side coil L13 and thesecondary coil L23 configure the on-chip transformer OCT3.

Fourth Embodiment

A configuration of a signal transmission module MD4 having asemiconductor device LSI401, a semiconductor device LSI402, asemiconductor device LSI41, and a semiconductor device LSI42 accordingto a fourth embodiment will be described with reference to FIG. 28.

The semiconductor device LSI41 includes the transmitter circuit TX1, thereceiver circuit RX1, and the heat generation determination unit EDET1,but does not include the on-chip transformer and the temperaturemonitoring unit. Likewise, the semiconductor device LSI42 includes thetransmitter circuit TX2, the receiver circuit RX2, and the heatgeneration determination unit EDET2, but does not include the on-chiptransformer and the temperature monitoring unit. The semiconductordevice LSI401 includes the on-chip transformer OCT1 and the temperaturemonitoring unit TS1. The semiconductor device LSI402 includes theon-chip transformer OCT2 and the temperature monitoring unit TS2.

The transmitter circuit TX1 of the semiconductor device LSI41 transmitsa signal to the receiver circuit RX2 of the semiconductor device LSI42through the on-chip transformer OCT1 of the semiconductor device LSI401.The transmitter circuit TX2 of the semiconductor device LSI42 transmitsa signal to the receiver circuit RX1 of the semiconductor device LSI41through the on-chip transformer OCT2 of the semiconductor device LSI402.

In the semiconductor device LSI401, the temperature monitoring unit TS1is arranged in the region immediately below or in the region adjacent tothe on-chip transformer OCT1. The forward voltage of the diode providedin the temperature monitoring unit TS1 is input to the heat generationdetermination unit EDET2 of the semiconductor device LSI42 through aline sa41, a line sc41, the pads 3, the bonding wires 1, and the linesa2 and the line sc2 of the semiconductor device LSI42. In thesemiconductor device LSI402, the temperature monitoring unit TS2 isarranged in the region immediately below or in the region adjacent tothe on-chip transformer OCT2. The forward voltage of the diode providedin the temperature monitoring unit TS2 is input to the heat generationdetermination unit EDET1 of the semiconductor device LSI41 through aline sa42, a line sc42, the bonding wires 1, and the line sa1 and theline sc1 of the semiconductor device LSI41. The heat generationdetermination unit EDET1 outputs the heat generation detection signalErr1 to the pads 3.

The semiconductor device LSI401 is configured by the temperaturemonitoring unit TS1 formed on the semiconductor substrate, and theon-chip transformer formed on the semiconductor substrate. Thesemiconductor device LSI402 is configured by the temperature monitoringunit TS2 formed on the semiconductor substrate, and the on-chiptransformer OCT2 formed on the semiconductor substrate. Therefore, thesemiconductor device LSI401 and the semiconductor device LSI402 can beprovided relatively inexpensively. Also, because the on-chip transformerand the temperature monitoring unit are mounted on a chip different fromthat of the semiconductor device LSI41 and the semiconductor deviceLSI42, this configuration can flexibly meet a variety of configurationrequests of the on-chip transformer and the temperature monitoring unit.

Fifth Embodiment

A configuration of a semiconductor device LSI5 according to a fifthembodiment will be described with reference to FIG. 29.

The semiconductor device LSI5 includes a first region 51 and a secondregion 52 which are formed of an SOI (silicon on insulator) layer on thesame substrate. The first region 51 and the second region 52 are formedwith a circuit that is applied with supply voltages VDD1/GND1, and acircuit that is applied with supply voltages VDD2/GND2, respectively.The first region 51 is formed with the on-chip transformer OCT1, thetransmitter circuit TX1, the receiver circuit RX1, the temperaturemonitoring unit TS1, and the heat generation determination unit EDET1.The second region 52 is formed with the on-chip transformer OCT2, thetransmitter circuit TX2, the receiver circuit RX2, the temperaturemonitoring unit TS2, and the heat generation determination unit EDET2.

The first region 51 and the second region 52 isolated from each other byan SOI technique are formed on the same substrate, thereby being capableof connecting the on-chip transformer OCT1, the transmitter circuit TX1,and the receiver circuit RX2 by the lines formed on the substrate.Likewise, the on-chip transformer OCT2, the transmitter circuit TX2, andthe receiver circuit RX1 can be connected by the lines formed on thesubstrate. As a result, a bonding wire that connects the circuits formedon the different chips becomes unnecessary, and the downsized signaltransmission module can be realized.

The on-chip transformer OCT1, the temperature monitoring unit TS1, andthe heat generation determination unit EDET1 installed in thesemiconductor device LSI1 mounted on the signal transmission module MD1according to the first embodiment have been mainly described above. Onthe other hand, the configuration of the on-chip transformer OCT2, thetemperature monitoring unit TS2, and the heat generation determinationunit EDET2 installed in the semiconductor device LSI2 mounted on thesignal transmission module MD1 according to the first embodiment is alsoidentical with that in the semiconductor device LSI1.

In the semiconductor device according to the respective embodiments, theon-chip transformer has the structure in which the different wiringlayers (the second wiring layer M2 and the fifth wiring layer M5) arevertically stacked on each other through the insulating film. Theconfiguration of the on-chip transformer is not limited to this example,but may be formed so that the wiring side portions face each otherthrough the insulating film in the same wiring layer.

Sixth Embodiment

A configuration of a signal transmission module MD6 having asemiconductor device LSI61 and a semiconductor device LSI62 according toa sixth embodiment will be described with reference to FIG. 30.

FIG. 30 is a perspective view schematically illustrating a configurationof the signal transmission module MD6 with a coupling capacitor C1 as anAC coupling element. The signal transmission module MD6 is a SiP inwhich the semiconductor device LSI61 and the semiconductor device LSI62are packed in one package. The Sip has multiple leads 2. The pads 3formed in the semiconductor device LSI61 and the semiconductor deviceLSI62 are electrically connected to the leads 2 by a bonding wire notshown. In order to avoid the troublesome drawings, the semiconductordevice LSI61 and the semiconductor device LSI62 are drawn in a statewhere the respective chip surfaces are exposed.

The semiconductor device LSI61 includes the transmitter circuit TX1, thecoupling capacitor. C1 which is an AC coupling element, the temperaturemonitoring unit TS1, and the heat generation determination unit EDET1.The coupling capacitor C1 includes a primary side capacitive electrodeCp1 which is any one of a first element and a second element, and asecondary side capacitive electrode Cp1 which is the other of the firstelement and the second element. An insulating film that forms adielectric is formed between both of the capacitive electrodes (notshown).

The transmitter circuit TX1 varies a potential of the primary sidecapacitive electrode Cp1 on the basis of an input signal supplied to thepads 3. The potential variation is transmitted as a potential variationof the secondary side capacitive electrode Cp2 by the capacitivecoupling. The semiconductor device LSI61 is applied with the supplyvoltage VDD1 and the supply voltage GND1. The temperature monitoringunit TS1 is formed on the semiconductor substrate in the regionimmediately below or in the region adjacent to the coupling capacitorC1.

The semiconductor device LS162 includes the receiver circuit RX1. Thereceiver circuit RX1 is applied with a voltage of the secondary sidecapacitive electrode Cp2 through the bonding wire 1 and the pad 3. Anoutput signal shaped into a desired waveform by the receiver circuit RX1is output to the leads 2 electrically connected to the pad 3 and abonding wire not shown. The semiconductor device LSI62 is applied withthe supply voltage VDD2 and the supply voltage GND2.

In the semiconductor device LSI61, a voltage between the anode and thecathode of a diode provided in the temperature monitoring unit TS1 isinput to the heat generation determination unit EDET1 through the linesa and the line sc. When the insulating film between the primary sidecapacitive electrode Cp1 and the secondary side capacitive electrode Cp2of the coupling capacitor C1 is broken down by a high voltage, theabnormal heat generation caused by the short-circuiting current betweenboth of the capacitive electrodes is generated. The heat generationdetermination unit EDET1 detects the temperature change of thesemiconductor substrate which is attributable to the abnormal heatgeneration, and inverts the logic level of the heat generation detectionsignal Err1.

Like the first embodiment, the diode provided in the temperaturemonitoring unit TS1 is arranged on the semiconductor substrate(immediately-below-region) immediately below a portion where the primaryside capacitive electrode Cp1 or the secondary side capacitive electrodeCp2 are formed, or in the outer periphery (adjacent region) of theimmediately-below-region.

The heat generation detection signal Err1 is output to the pads 3, andalso output to the control circuit CTL1 (not shown) as in thesemiconductor device LSI1 illustrated in FIG. 2. The heat generationdetection signal Err1 output to the pad 3 is input to the microcomputerMCU (not shown) that controls the operation of the semiconductor deviceLSI61. On the other hand, the heat generation detection signal Err1output to the control circuit CTL1 controls the operation of thetransmitter circuit TX1. The protection operation by the heat generationdetection signal Err1 is identical with that in the first embodiment,and a description thereof is not repeated.

Referring to FIG. 30, the coupling capacitor C1 and the transmittercircuit TX1 are each formed in the semiconductor device LSI61. However,the layout of the coupling capacitor C1 is not limited to thatconfiguration. Instead of the coupling capacitor C1 being formed in thesemiconductor device LSI61, the coupling capacitor C1 may be formed inthe semiconductor device LSI62 together with the receiver circuit RX1.In this case, the temperature monitoring unit TS1 and the heatgeneration determination unit EDET1 are formed in the semiconductordevice LS162.

The primary side capacitive electrode Cp1 and the secondary sidecapacitive electrode Cp2 configuring the coupling capacitor C1 arestructured to be stacked on each other in parallel to the semiconductorsubstrate surface, and through an insulating film acting as a dielectrictherebetween. The structure of the coupling capacitor C1 is not limitedto the structure in which the plate electrode is arranged in parallel tothe semiconductor substrate. For example, the primary side capacitiveelectrode Cp1 and the secondary side capacitive electrode Cp2 may bearranged to face each other through the insulating film in a directionperpendicular to the semiconductor substrate.

It should be conceivable that the embodiments disclosed at present areentirely exemplary, and not restrictive. The scope of the presentinvention is defined not by the above description, but by the claims,and intended to include the meanings equivalent to the claims, and allof the changes within the scope of the claims.

1-20. (canceled)
 21. A semiconductor device, comprising: an AC coupling element that is formed on a semiconductor substrate; a temperature monitoring unit that outputs a temperature monitor signal in response to a change in a temperature of the semiconductor substrate; a heat generation determination unit that outputs a heat generation detection signal on the basis of the temperature monitor signal; a power supply pad that applies a supply voltage; and a transmitter circuit that is coupled to the AC coupling element, wherein the temperature monitoring unit includes a first temperature monitoring element that outputs the temperature monitor signal, and wherein the first temperature monitoring element is arranged in a region below or a region adjacent to the AC coupling element.
 22. The semiconductor device according to claim 21, wherein the temperature monitoring unit further includes a second temperature monitoring element, wherein the second temperature monitoring element is arranged in a region below or in a region adjacent to the AC coupling element, and coupled in parallel to the first temperature monitoring element.
 23. A semiconductor device, comprising: an AC coupling element that is formed on a semiconductor substrate; a temperature monitoring unit that outputs a temperature monitor signal in response to a change in a temperature of the semiconductor substrate; a heat generation determination unit that outputs a heat generation detection signal on the basis of the temperature monitor signal; a power supply pad that applies a supply voltage; and a receiver circuit that is connected to the AC coupling element, wherein the temperature monitoring unit includes a first temperature monitoring element that outputs the temperature monitor signal, wherein the first temperature monitoring element is arranged in a region below or a region adjacent to the AC coupling element, wherein the heat generation determination unit includes a comparator, wherein the comparator outputs the heat generation detection signal on the basis of a comparison result between a reference voltage and the temperature monitor signal, and wherein a resistance value of a power supply line between the power supply pad and the comparator is smaller than a resistance value between the power supply pad and the receiver circuit.
 24. The semiconductor device according to claim 21, further comprising: a temperature detection unit that activates an overheat protection function, wherein the reference voltage is larger than a reference voltage which is applied to the temperature detection unit.
 25. The semiconductor device according to claim 21, further comprising: a reference temperature detection element, wherein a distance between the reference temperature detection element and the AC coupling element is larger than a distance between the temperature monitoring unit and the AC coupling element, and wherein the reference temperature detection element generates the reference voltage.
 26. The semiconductor device according to claim 21, wherein the temperature monitoring unit is arranged adjacent to a transmission driver circuit of the transmitter circuit.
 27. The semiconductor device according to claim 23, wherein the temperature monitoring unit is arranged adjacent to the receiver circuit.
 28. The semiconductor device according to claim 21, wherein a distance between the AC coupling element and the heat generation determination unit is larger than a distance between the AC coupling element and the temperature monitoring unit.
 29. The semiconductor device according to claim 28, wherein the AC coupling element is an on-chip transformer or a coupling capacitor.
 30. A semiconductor device, comprising: a temperature monitoring unit that includes a first temperature monitoring element formed on a semiconductor substrate; and an AC coupling element that includes a first element and a second element formed on the semiconductor substrate, wherein the first element and the second element are arranged to perform AC coupling, and wherein the first temperature monitoring element is arranged in a region below or in a region adjacent to a formation region of the AC coupling element, wherein the first element includes a first coil which is formed of a first wiring layer, wherein the second element includes a second coil which is formed of a second wiring layer different from the first wiring layer, and wherein the first temperature monitoring element formed in the region adjacent to the AC coupling element is covered with a shield layer formed of the lower wiring layer of the first wiring layer and the second wiring layer.
 31. The semiconductor device according to claim 30, wherein the first element includes a third coil which is formed of a third wiring layer, and wherein the second element includes a fourth coil which is formed of the third wiring layer.
 32. The semiconductor device according to claim 30, wherein the first element includes a first capacitive electrode, and wherein the second element includes a second capacitive electrode.
 33. The semiconductor device according to claim 30, wherein the temperature monitoring unit further includes a second temperature monitoring element which is formed on the semiconductor substrate, and wherein the second temperature monitoring element is arranged in a region below or in a region adjacent to the AC coupling element, and coupled in parallel to the first temperature monitoring element. 